Searched refs:uart_setreg (Results 1 - 19 of 19) sorted by relevance

/freebsd-11-stable/sys/dev/uart/
H A Duart_dev_sab82532.c110 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XRES);
116 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RRES);
152 uart_setreg(bas, SAB_BGR, divisor & 0xff);
155 uart_setreg(bas, SAB_TCR, divisor & 0xff);
160 uart_setreg(bas, SAB_CCR2, ccr2);
164 uart_setreg(bas, SAB_DAFO, dafo);
209 uart_setreg(bas, SAB_PCR,
213 uart_setreg(bas, SAB_PIM, 0xff);
216 uart_setreg(bas, SAB_IPC, SAB_IPC_ICPL);
228 uart_setreg(ba
[all...]
H A Duart_dev_ns8250.c111 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
115 uart_setreg(bas, REG_LCR, lcr);
208 uart_setreg(bas, REG_FCR, fcr);
237 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
239 uart_setreg(bas, REG_DLL, divisor & 0xff);
240 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
245 uart_setreg(bas, REG_LCR, lcr);
308 uart_setreg(bas, REG_IER, ier);
312 uart_setreg(bas, REG_FCR, 0);
316 uart_setreg(ba
[all...]
H A Duart_dev_lpc.c199 uart_setreg(bas, REG_FCR, fcr);
225 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
227 uart_setreg(bas, REG_DLL, 0x00);
228 uart_setreg(bas, REG_DLH, 0x00);
239 uart_setreg(bas, REG_LCR, lcr);
302 uart_setreg(bas, REG_DATA, 0x00);
315 uart_setreg(bas, REG_IER, ier);
319 uart_setreg(bas, REG_FCR, 0);
323 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
334 uart_setreg(ba
[all...]
H A Duart_dev_msm.c124 uart_setreg(bas, UART_DM_MR2, ulcon);
127 uart_setreg(bas, UART_DM_CSR, UART_DM_CSR_115200);
166 uart_setreg(bas, UART_DM_MR1, 0x0);
169 uart_setreg(bas, UART_DM_IMR, 0);
176 uart_setreg(bas, UART_DM_TFWR, UART_DM_TFW_VALUE);
179 uart_setreg(bas, UART_DM_RFWR, UART_DM_RFW_VALUE);
185 uart_setreg(bas, UART_DM_IPR, UART_DM_STALE_TIMEOUT_LSB);
188 uart_setreg(bas, UART_DM_IRDA, 0x0);
195 uart_setreg(bas, UART_DM_HCR, 0x0);
206 uart_setreg(ba
[all...]
H A Duart_dev_ti8250.c92 uart_setreg(&sc->sc_bas, MDR1_REG, MDR1_MODE_DISABLE);
93 uart_setreg(&sc->sc_bas, SYSCC_REG, SYSCC_SOFTRESET);
96 uart_setreg(&sc->sc_bas, MDR1_REG, MDR1_MODE_UART);
H A Duart_dev_z8530.c58 uart_setreg(bas, REG_CTRL, reg);
60 uart_setreg(bas, REG_CTRL, val);
67 uart_setreg(bas, REG_CTRL, reg);
233 uart_setreg(bas, REG_DATA, c);
457 uart_setreg(bas, REG_CTRL, CR_RSTTXI);
466 uart_setreg(bas, REG_CTRL, CR_RSTXSI);
479 uart_setreg(bas, REG_CTRL, CR_RSTERR);
486 uart_setreg(bas, REG_CTRL, CR_RSTIUS);
556 uart_setreg(bas, REG_CTRL, CR_RSTERR);
567 uart_setreg(ba
[all...]
H A Duart.h53 #define uart_setreg(bas, reg, value) \ macro
/freebsd-11-stable/sys/mips/cavium/
H A Duart_dev_oct16550.c116 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
120 uart_setreg(bas, REG_LCR, lcr);
217 uart_setreg(bas, REG_FCR, fcr);
246 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
248 uart_setreg(bas, REG_DLL, divisor & 0xff);
249 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
255 uart_setreg(bas, REG_LCR, lcr);
307 uart_setreg(bas, REG_IER, ier);
311 // uart_setreg(bas, REG_FCR, 0);
315 uart_setreg(ba
[all...]
/freebsd-11-stable/sys/arm/amlogic/aml8726/
H A Duart_dev_aml8726.c66 #undef uart_setreg macro
70 #define uart_setreg(bas, reg, value) \ macro
166 uart_setreg(bas, AML_UART_NEW_BAUD_REG, nbr);
186 uart_setreg(bas, AML_UART_MISC_REG, mr);
189 uart_setreg(bas, AML_UART_CONTROL_REG, cr);
222 uart_setreg(bas, AML_UART_CONTROL_REG, cr);
228 uart_setreg(bas, AML_UART_MISC_REG, mr);
233 uart_setreg(bas, AML_UART_CONTROL_REG, cr);
250 uart_setreg(bas, AML_UART_WFIFO_REG, c);
411 uart_setreg(ba
[all...]
/freebsd-11-stable/sys/arm/allwinner/
H A Dconsole.c63 uart_setreg(uint32_t *bas, uint32_t val) function
88 uart_setreg((uint32_t *)A10_UART_BASE, c);
120 uart_setreg((uint32_t *)(A10_UART_BASE +
/freebsd-11-stable/sys/arm/freescale/vybrid/
H A Dvf_uart.c159 uart_setreg(bas, UART_D, c);
212 uart_setreg(bas, UART_MODEM, 0x00);
220 uart_setreg(bas, UART_C2, 0x00);
222 uart_setreg(bas, UART_C1, 0x00);
230 uart_setreg(bas, UART_BDH, reg);
233 uart_setreg(bas, UART_BDL, reg);
238 uart_setreg(bas, UART_C4, reg);
242 uart_setreg(bas, UART_C2, reg);
308 uart_setreg(bas, UART_C2, reg);
382 uart_setreg(ba
[all...]
/freebsd-11-stable/sys/mips/mediatek/
H A Duart_dev_mtk.c126 uart_setreg(bas, UART_CDDL_REG, bas->rclk/16/baudrate);
130 uart_setreg(bas, UART_LCR_REG, databits |
139 uart_setreg(bas, UART_MCR_REG, 0);
150 uart_setreg(bas, UART_TX_REG, c);
262 uart_setreg(bas, UART_IER_REG, cr);
277 uart_setreg(bas, UART_IER_REG, cr);
308 uart_setreg(bas, UART_FCR_REG,
314 uart_setreg(bas, UART_IER_REG,
334 uart_setreg(bas, UART_FCR_REG, fcr|UART_FCR_TXRST);
338 uart_setreg(ba
[all...]
H A Duart_dev_mtk.h37 #undef uart_setreg macro
40 #define uart_setreg(bas, reg, value) \ macro
/freebsd-11-stable/sys/mips/rt305x/
H A Duart_dev_rt305x.c117 uart_setreg(bas, UART_CDDL_REG, 8000000/baudrate);
119 uart_setreg(bas, UART_LCR_REG, databits | (stopbits==1?0:4) | parity);
127 uart_setreg(bas, UART_MCR_REG, 0);
138 uart_setreg(bas, UART_TX_REG, c);
242 uart_setreg(bas, UART_IER_REG, cr);
257 uart_setreg(bas, UART_IER_REG, cr);
279 uart_setreg(bas, UART_FCR_REG,
284 uart_setreg(bas, UART_IER_REG,
304 uart_setreg(bas, UART_FCR_REG, fcr|UART_FCR_TXRST);
308 uart_setreg(ba
[all...]
H A Duart_dev_rt305x.h37 #undef uart_setreg macro
40 #define uart_setreg(bas, reg, value) \ macro
/freebsd-11-stable/sys/mips/adm5120/
H A Duart_dev_adm5120.c99 uart_setreg(bas, UART_DR_REG, c);
199 uart_setreg(&sc->sc_bas, UART_CR_REG, cr);
212 uart_setreg(&sc->sc_bas, UART_CR_REG, cr);
233 uart_setreg(bas, UART_LCR_H_REG,
237 uart_setreg(bas, UART_CR_REG,
345 uart_setreg(bas, UART_IR_REG, ir | UART_IR_UICR);
410 uart_setreg(bas, UART_ECR_REG, UART_ECR_RSR);
422 uart_setreg(bas, UART_ECR_REG, UART_ECR_RSR);
450 uart_setreg(bas, UART_DR_REG, sc->sc_txbuf[i]);
465 uart_setreg(
[all...]
/freebsd-11-stable/sys/arm/samsung/exynos/
H A Dexynos_uart.c122 uart_setreg(bas, SSCOM_ULCON, ulcon);
125 uart_setreg(bas, SSCOM_UBRDIV, brd);
156 uart_setreg(bas, SSCOM_UCON, 0);
157 uart_setreg(bas, SSCOM_UFCON,
164 uart_setreg(bas, SSCOM_UCON, UCON_TXMODE_INT | UCON_RXMODE_INT |
166 uart_setreg(bas, SSCOM_UMCON, UMCON_RTS);
183 uart_setreg(bas, SSCOM_UTXH, c);
/freebsd-11-stable/sys/arm/nvidia/
H A Dtegra_uart.c86 uart_setreg(bas, REG_IER, ns8250->ier);
105 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);
106 uart_setreg(bas, REG_FCR, 0);
121 uart_setreg(bas, REG_FCR, ns8250->fcr);
122 uart_setreg(bas, REG_IER, ns8250->ier);
/freebsd-11-stable/sys/mips/atheros/
H A Duart_dev_ar933x.c649 uart_setreg(bas, REG_MCR, ns8250->mcr);

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