| /freebsd-11-stable/sys/dev/sio/ |
| H A D | sio_puc.c | 68 uintptr_t rclk; local
71 &rclk) != 0)
72 rclk = DEFAULT_RCLK;
73 return (sioattach(dev, 0, rclk));
80 uintptr_t rclk, type; local
90 if (BUS_READ_IVAR(parent, dev, PUC_IVAR_CLOCK, &rclk))
91 rclk = DEFAULT_RCLK;
95 error = sioprobe(dev, 0, rclk, 1);
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| H A D | siovar.h | 62 int sioattach(device_t dev, int xrid, u_long rclk);
64 int sioprobe(device_t dev, int xrid, u_long rclk, int noprobe);
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| /freebsd-11-stable/sys/arm/xscale/ixp425/ |
| H A D | uart_bus_ixp425.c | 72 u_int rclk; local
76 if (resource_int_value("uart", unit, "rclk", &rclk))
77 rclk = IXP425_UART_FREQ;
79 device_printf(dev, "rclk %u\n", rclk);
81 return uart_bus_probe(dev, 0, 0, rclk, 0, 0, 0);
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| H A D | uart_cpu_ixp425.c | 82 di->bas.rclk = IXP425_UART_FREQ;
|
| /freebsd-11-stable/sys/dev/scc/ |
| H A D | scc_bfe_quicc.c | 50 uintptr_t devtype, rclk; local
65 if (BUS_READ_IVAR(parent, dev, QUICC_IVAR_BRGCLK, &rclk))
66 rclk = 0;
67 return (scc_bfe_probe(dev, 0, rclk, 0));
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| H A D | scc_bfe.h | 36 * to access the SCC. The rclk field, although not important to actually
44 u_int rclk; member in struct:scc_bas
143 int scc_bfe_probe(device_t dev, u_int regshft, u_int rclk, u_int rid);
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| /freebsd-11-stable/sys/dev/uart/ |
| H A D | uart_bus_puc.c | 70 uintptr_t rclk, type; local
82 if (BUS_READ_IVAR(parent, dev, PUC_IVAR_CLOCK, &rclk))
83 rclk = 0;
84 return (uart_bus_probe(dev, 0, 0, rclk, 0, 0, 0));
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| H A D | uart_cpu_fdt.c | 79 u_int shift, rclk; local
91 err = uart_cpu_fdt_probe(&class, &bst, &bsh, &br, &rclk, &shift);
101 di->bas.rclk = rclk;
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| H A D | uart_cpu_powerpc.c | 189 if (OF_getprop(input, "clock-frequency", &di->bas.rclk,
190 sizeof(di->bas.rclk)) == -1)
191 di->bas.rclk = 230400;
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| H A D | uart_cpu_x86.c | 96 di->bas.rclk = 0;
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| H A D | uart.h | 34 * to access the UART. The rclk field, although not important to actually
42 u_int rclk; member in struct:uart_bas
|
| /freebsd-11-stable/sys/arm/samsung/exynos/ |
| H A D | exynos_uart.c | 124 brd = sscomspeed(baudrate, bas->rclk);
151 if (bas->rclk == 0)
152 bas->rclk = DEF_CLK;
154 KASSERT(bas->rclk != 0, ("exynos4210_init: Invalid rclk"));
305 if (sc->sc_bas.rclk == 0)
306 sc->sc_bas.rclk = DEF_CLK;
308 KASSERT(sc->sc_bas.rclk != 0, ("exynos4210_init: Invalid rclk"));
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| /freebsd-11-stable/sys/arm/xscale/pxa/ |
| H A D | uart_cpu_pxa.c | 60 di->bas.rclk = PXA2X0_COM_FREQ;
|
| /freebsd-11-stable/sys/arm/at91/ |
| H A D | uart_cpu_at91usart.c | 80 di->bas.rclk = 0;
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| /freebsd-11-stable/sys/arm/cavium/cns11xx/ |
| H A D | uart_cpu_ec.c | 76 di->bas.rclk = EC_UART_CLOCK ;
|
| /freebsd-11-stable/sys/mips/adm5120/ |
| H A D | uart_cpu_adm5120.c | 72 di->bas.rclk = 0;
|
| /freebsd-11-stable/sys/mips/alchemy/ |
| H A D | uart_cpu_alchemy.c | 68 di->bas.rclk = 0;
|
| /freebsd-11-stable/sys/mips/atheros/ |
| H A D | uart_cpu_ar71xx.c | 65 di->bas.rclk = freq;
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| H A D | uart_cpu_ar933x.c | 67 di->bas.rclk = freq;
|
| /freebsd-11-stable/sys/mips/idt/ |
| H A D | uart_cpu_rc32434.c | 76 di->bas.rclk = 330000000UL/2; /* IPbus clock */
|
| /freebsd-11-stable/sys/mips/malta/ |
| H A D | uart_cpu_maltausart.c | 69 di->bas.rclk = 0;
|
| /freebsd-11-stable/sys/mips/nlm/ |
| H A D | uart_cpu_xlp.c | 84 /* divisor = rclk / (baudrate * 16); */
85 di->bas.rclk = XLP_IO_CLK;
|
| /freebsd-11-stable/sys/mips/rmi/ |
| H A D | uart_cpu_mips_xlr.c | 74 /* divisor = rclk / (baudrate * 16); */
75 di->bas.rclk = 66000000;
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| /freebsd-11-stable/sys/mips/rt305x/ |
| H A D | uart_cpu_rt305x.c | 71 di->bas.rclk = SYSTEM_CLOCK;
|
| /freebsd-11-stable/sys/arm/xscale/i8134x/ |
| H A D | uart_cpu_i81342.c | 59 di->bas.rclk = 33334000;
|