Searched refs:lanes (Results 1 - 16 of 16) sorted by relevance

/freebsd-11-stable/sys/contrib/octeon-sdk/
H A Dcvmx-helper-ilk.c112 /* configure lanes and enable the link */
320 int lanes = 0; local
373 lanes = cvmx_pop(ilk_rxx_cfg1.s.rx_bdry_lock_ena);
378 result.s.speed *= lanes;
389 //cvmx_dprintf("ILK%d: link up, %d Mbps, Full duplex mode, %d lanes\n", interface, result.s.speed, lanes);
H A Dcvmx-helper-xaui.c375 int lanes; local
380 lanes = (qlm_cfg.s.qlm_cfg == 7) ? 2 : 4;
381 result.s.speed *= lanes;
/freebsd-11-stable/sys/dev/nvme/
H A Dnvme_sim.c131 uint32_t speed, lanes, link[] = { 1, 250000, 500000, 985000, 1970000 }; local
136 lanes = (status & PCIEM_LINK_STA_WIDTH) >> 4;
139 * lanes as the speed. Not 100% accurate, but may be diagnostic.
143 return link[speed] * lanes;
240 nvmex->lanes = (status & PCIEM_LINK_STA_WIDTH) >> 4;
/freebsd-11-stable/sys/dev/drm2/i915/
H A Dintel_bios.c532 switch (edp_link_params->lanes) {
534 dev_priv->edp.lanes = 1;
537 dev_priv->edp.lanes = 2;
541 dev_priv->edp.lanes = 4;
H A Dintel_bios.h465 u8 lanes:4; member in struct:edp_link_params
H A Di915_drv.h723 int lanes; member in struct:drm_i915_private::__anon9875
/freebsd-11-stable/sys/contrib/alpine-hal/
H A Dal_hal_pcie.h75 * - set number of lanes connected to the controller.
87 * - Set the max lanes width to 2 (x2)
353 struct al_pcie_gen3_lane_eq_params *eq_params; /* array of lanes params */
484 uint8_t lanes; member in struct:al_pcie_link_status
581 * Configure number of lanes connected to this port.
585 * @param lanes number of lanes
590 int al_pcie_port_max_lanes_set(struct al_pcie_port *pcie_port, uint8_t lanes);
H A Dal_hal_pcie.c186 al_dbg("PCIe %d: link config: max speed gen %d, max lanes %d, reversal %s\n",
202 * Link Mode Enable. Sets the number of lanes in the link that you want
203 * to connect to the link partner. When you have unused lanes in your
205 * the number of lanes. You must also change the value in the
1362 al_pcie_port_max_lanes_set(struct al_pcie_port *pcie_port, uint8_t lanes) argument
1367 al_err("PCIe %d: already enabled, cannot set max lanes\n",
1373 uint32_t active_lanes_val = AL_PCIE_PARSE_LANES(lanes);
1381 pcie_port->max_lanes = lanes;
1635 /* if max lanes not specifies, read it from register */
1659 al_err("PCIe %d: invalid max lanes va
[all...]
/freebsd-11-stable/sys/dev/drm2/radeon/
H A Drv770.c1224 u32 link_width_cntl, lanes, speed_cntl, tmp; local
1257 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1260 link_width_cntl |= lanes | LC_RECONFIG_NOW |
H A Dradeon_asic.h173 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
353 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
H A Dr300.c469 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) argument
481 switch (lanes) {
H A Dr600.c4142 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) argument
4158 switch (lanes) {
4261 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; local
4308 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4311 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
H A Dradeon.h1060 int pcie_lanes; /* pcie lanes */
1285 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
/freebsd-11-stable/contrib/llvm-project/clang/utils/TableGen/
H A DMveEmitter.cpp120 // same number of lanes as the input vector type. So our Predicate type
290 unsigned lanes() const { return Lanes; } function in class:__anon961::VectorType
1071 cast<VectorType>(ExistingVector)->lanes());
1457 OS << "typedef __attribute__((neon_vector_type(" << VT->lanes() << "))) "
/freebsd-11-stable/sys/arm/nvidia/tegra124/
H A Dtegra124_xusbpadctl.c266 struct padctl_lane *lanes[8]; /* Safe maximum value. */ member in struct:padctl_pad
336 /* Define all possible mappings for USB3 port lanes */
821 " lanes: %s and %s\n", lane->name, tmp->name);
915 pad->lanes[pad->nlanes++] = lane;
962 /* Read and process associated lanes. */
963 node = ofw_bus_find_child(node, "lanes");
/freebsd-11-stable/sys/cam/
H A Dcam_ccb.h1010 uint8_t lanes; /* Number of PCIe lanes */ member in struct:ccb_trans_settings_nvme
1012 uint8_t max_lanes; /* Number of PCIe lanes */

Completed in 307 milliseconds