1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD$"); 31 32#ifndef __RADEON_ASIC_H__ 33#define __RADEON_ASIC_H__ 34 35/* 36 * common functions 37 */ 38uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 39void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 40uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); 41void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 42 43uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 44void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 45uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); 46void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 47void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 48 49void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 50u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); 51void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 52u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); 53 54 55/* 56 * r100,rv100,rs100,rv200,rs200 57 */ 58struct r100_mc_save { 59 u32 GENMO_WT; 60 u32 CRTC_EXT_CNTL; 61 u32 CRTC_GEN_CNTL; 62 u32 CRTC2_GEN_CNTL; 63 u32 CUR_OFFSET; 64 u32 CUR2_OFFSET; 65}; 66int r100_init(struct radeon_device *rdev); 67void r100_fini(struct radeon_device *rdev); 68int r100_suspend(struct radeon_device *rdev); 69int r100_resume(struct radeon_device *rdev); 70void r100_vga_set_state(struct radeon_device *rdev, bool state); 71bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 72int r100_asic_reset(struct radeon_device *rdev); 73u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 74void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 75int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 76void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 77int r100_irq_set(struct radeon_device *rdev); 78irqreturn_t r100_irq_process(struct radeon_device *rdev); 79void r100_fence_ring_emit(struct radeon_device *rdev, 80 struct radeon_fence *fence); 81void r100_semaphore_ring_emit(struct radeon_device *rdev, 82 struct radeon_ring *cp, 83 struct radeon_semaphore *semaphore, 84 bool emit_wait); 85int r100_cs_parse(struct radeon_cs_parser *p); 86void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 87uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); 88int r100_copy_blit(struct radeon_device *rdev, 89 uint64_t src_offset, 90 uint64_t dst_offset, 91 unsigned num_gpu_pages, 92 struct radeon_fence **fence); 93int r100_set_surface_reg(struct radeon_device *rdev, int reg, 94 uint32_t tiling_flags, uint32_t pitch, 95 uint32_t offset, uint32_t obj_size); 96void r100_clear_surface_reg(struct radeon_device *rdev, int reg); 97void r100_bandwidth_update(struct radeon_device *rdev); 98void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 99int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 100void r100_hpd_init(struct radeon_device *rdev); 101void r100_hpd_fini(struct radeon_device *rdev); 102bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 103void r100_hpd_set_polarity(struct radeon_device *rdev, 104 enum radeon_hpd_id hpd); 105int r100_debugfs_rbbm_init(struct radeon_device *rdev); 106int r100_debugfs_cp_init(struct radeon_device *rdev); 107void r100_cp_disable(struct radeon_device *rdev); 108int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 109void r100_cp_fini(struct radeon_device *rdev); 110int r100_pci_gart_init(struct radeon_device *rdev); 111void r100_pci_gart_fini(struct radeon_device *rdev); 112int r100_pci_gart_enable(struct radeon_device *rdev); 113void r100_pci_gart_disable(struct radeon_device *rdev); 114int r100_debugfs_mc_info_init(struct radeon_device *rdev); 115int r100_gui_wait_for_idle(struct radeon_device *rdev); 116int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 117void r100_irq_disable(struct radeon_device *rdev); 118void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 119void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 120void r100_vram_init_sizes(struct radeon_device *rdev); 121int r100_cp_reset(struct radeon_device *rdev); 122void r100_vga_render_disable(struct radeon_device *rdev); 123void r100_restore_sanity(struct radeon_device *rdev); 124int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 125 struct radeon_cs_packet *pkt, 126 struct radeon_bo *robj); 127int r100_cs_parse_packet0(struct radeon_cs_parser *p, 128 struct radeon_cs_packet *pkt, 129 const unsigned *auth, unsigned n, 130 radeon_packet0_check_t check); 131int r100_cs_packet_parse(struct radeon_cs_parser *p, 132 struct radeon_cs_packet *pkt, 133 unsigned idx); 134void r100_enable_bm(struct radeon_device *rdev); 135void r100_set_common_regs(struct radeon_device *rdev); 136void r100_bm_disable(struct radeon_device *rdev); 137extern bool r100_gui_idle(struct radeon_device *rdev); 138extern void r100_pm_misc(struct radeon_device *rdev); 139extern void r100_pm_prepare(struct radeon_device *rdev); 140extern void r100_pm_finish(struct radeon_device *rdev); 141extern void r100_pm_init_profile(struct radeon_device *rdev); 142extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); 143extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); 144extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 145extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); 146extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); 147extern int r100_mc_wait_for_idle(struct radeon_device *rdev); 148 149/* 150 * r200,rv250,rs300,rv280 151 */ 152extern int r200_copy_dma(struct radeon_device *rdev, 153 uint64_t src_offset, 154 uint64_t dst_offset, 155 unsigned num_gpu_pages, 156 struct radeon_fence **fence); 157void r200_set_safe_registers(struct radeon_device *rdev); 158 159/* 160 * r300,r350,rv350,rv380 161 */ 162extern int r300_init(struct radeon_device *rdev); 163extern void r300_fini(struct radeon_device *rdev); 164extern int r300_suspend(struct radeon_device *rdev); 165extern int r300_resume(struct radeon_device *rdev); 166extern int r300_asic_reset(struct radeon_device *rdev); 167extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 168extern void r300_fence_ring_emit(struct radeon_device *rdev, 169 struct radeon_fence *fence); 170extern int r300_cs_parse(struct radeon_cs_parser *p); 171extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); 172extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 173extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 174extern int rv370_get_pcie_lanes(struct radeon_device *rdev); 175extern void r300_set_reg_safe(struct radeon_device *rdev); 176extern void r300_mc_program(struct radeon_device *rdev); 177extern void r300_mc_init(struct radeon_device *rdev); 178extern void r300_clock_startup(struct radeon_device *rdev); 179extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 180extern int rv370_pcie_gart_init(struct radeon_device *rdev); 181extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 182extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 183extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 184 185/* 186 * r420,r423,rv410 187 */ 188extern int r420_init(struct radeon_device *rdev); 189extern void r420_fini(struct radeon_device *rdev); 190extern int r420_suspend(struct radeon_device *rdev); 191extern int r420_resume(struct radeon_device *rdev); 192extern void r420_pm_init_profile(struct radeon_device *rdev); 193extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 194extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 195extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 196extern void r420_pipes_init(struct radeon_device *rdev); 197 198/* 199 * rs400,rs480 200 */ 201extern int rs400_init(struct radeon_device *rdev); 202extern void rs400_fini(struct radeon_device *rdev); 203extern int rs400_suspend(struct radeon_device *rdev); 204extern int rs400_resume(struct radeon_device *rdev); 205void rs400_gart_tlb_flush(struct radeon_device *rdev); 206int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 207uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 208void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 209int rs400_gart_init(struct radeon_device *rdev); 210int rs400_gart_enable(struct radeon_device *rdev); 211void rs400_gart_adjust_size(struct radeon_device *rdev); 212void rs400_gart_disable(struct radeon_device *rdev); 213void rs400_gart_fini(struct radeon_device *rdev); 214extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); 215 216/* 217 * rs600. 218 */ 219extern int rs600_asic_reset(struct radeon_device *rdev); 220extern int rs600_init(struct radeon_device *rdev); 221extern void rs600_fini(struct radeon_device *rdev); 222extern int rs600_suspend(struct radeon_device *rdev); 223extern int rs600_resume(struct radeon_device *rdev); 224int rs600_irq_set(struct radeon_device *rdev); 225irqreturn_t rs600_irq_process(struct radeon_device *rdev); 226void rs600_irq_disable(struct radeon_device *rdev); 227u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 228void rs600_gart_tlb_flush(struct radeon_device *rdev); 229int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 230uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 231void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 232void rs600_bandwidth_update(struct radeon_device *rdev); 233void rs600_hpd_init(struct radeon_device *rdev); 234void rs600_hpd_fini(struct radeon_device *rdev); 235bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 236void rs600_hpd_set_polarity(struct radeon_device *rdev, 237 enum radeon_hpd_id hpd); 238extern void rs600_pm_misc(struct radeon_device *rdev); 239extern void rs600_pm_prepare(struct radeon_device *rdev); 240extern void rs600_pm_finish(struct radeon_device *rdev); 241extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); 242extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 243extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); 244void rs600_set_safe_registers(struct radeon_device *rdev); 245extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); 246extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); 247 248/* 249 * rs690,rs740 250 */ 251int rs690_init(struct radeon_device *rdev); 252void rs690_fini(struct radeon_device *rdev); 253int rs690_resume(struct radeon_device *rdev); 254int rs690_suspend(struct radeon_device *rdev); 255uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 256void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 257void rs690_bandwidth_update(struct radeon_device *rdev); 258void rs690_line_buffer_adjust(struct radeon_device *rdev, 259 struct drm_display_mode *mode1, 260 struct drm_display_mode *mode2); 261extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); 262 263/* 264 * rv515 265 */ 266struct rv515_mc_save { 267 u32 vga_render_control; 268 u32 vga_hdp_control; 269 bool crtc_enabled[2]; 270}; 271 272int rv515_init(struct radeon_device *rdev); 273void rv515_fini(struct radeon_device *rdev); 274uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 275void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 276void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 277void rv515_bandwidth_update(struct radeon_device *rdev); 278int rv515_resume(struct radeon_device *rdev); 279int rv515_suspend(struct radeon_device *rdev); 280void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 281void rv515_vga_render_disable(struct radeon_device *rdev); 282void rv515_set_safe_registers(struct radeon_device *rdev); 283void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 284void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 285void rv515_clock_startup(struct radeon_device *rdev); 286void rv515_debugfs(struct radeon_device *rdev); 287int rv515_mc_wait_for_idle(struct radeon_device *rdev); 288 289/* 290 * r520,rv530,rv560,rv570,r580 291 */ 292int r520_init(struct radeon_device *rdev); 293int r520_resume(struct radeon_device *rdev); 294int r520_mc_wait_for_idle(struct radeon_device *rdev); 295 296/* 297 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 298 */ 299int r600_init(struct radeon_device *rdev); 300void r600_fini(struct radeon_device *rdev); 301int r600_suspend(struct radeon_device *rdev); 302int r600_resume(struct radeon_device *rdev); 303void r600_vga_set_state(struct radeon_device *rdev, bool state); 304int r600_wb_init(struct radeon_device *rdev); 305void r600_wb_fini(struct radeon_device *rdev); 306void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 307uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 308void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 309int r600_cs_parse(struct radeon_cs_parser *p); 310int r600_dma_cs_parse(struct radeon_cs_parser *p); 311void r600_fence_ring_emit(struct radeon_device *rdev, 312 struct radeon_fence *fence); 313void r600_semaphore_ring_emit(struct radeon_device *rdev, 314 struct radeon_ring *cp, 315 struct radeon_semaphore *semaphore, 316 bool emit_wait); 317void r600_dma_fence_ring_emit(struct radeon_device *rdev, 318 struct radeon_fence *fence); 319void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 320 struct radeon_ring *ring, 321 struct radeon_semaphore *semaphore, 322 bool emit_wait); 323void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 324bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 325bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 326int r600_asic_reset(struct radeon_device *rdev); 327int r600_set_surface_reg(struct radeon_device *rdev, int reg, 328 uint32_t tiling_flags, uint32_t pitch, 329 uint32_t offset, uint32_t obj_size); 330void r600_clear_surface_reg(struct radeon_device *rdev, int reg); 331int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 332int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 333void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 334int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 335int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 336int r600_copy_blit(struct radeon_device *rdev, 337 uint64_t src_offset, uint64_t dst_offset, 338 unsigned num_gpu_pages, struct radeon_fence **fence); 339int r600_copy_dma(struct radeon_device *rdev, 340 uint64_t src_offset, uint64_t dst_offset, 341 unsigned num_gpu_pages, struct radeon_fence **fence); 342void r600_hpd_init(struct radeon_device *rdev); 343void r600_hpd_fini(struct radeon_device *rdev); 344bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 345void r600_hpd_set_polarity(struct radeon_device *rdev, 346 enum radeon_hpd_id hpd); 347extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); 348extern bool r600_gui_idle(struct radeon_device *rdev); 349extern void r600_pm_misc(struct radeon_device *rdev); 350extern void r600_pm_init_profile(struct radeon_device *rdev); 351extern void rs780_pm_init_profile(struct radeon_device *rdev); 352extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); 353extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); 354extern int r600_get_pcie_lanes(struct radeon_device *rdev); 355bool r600_card_posted(struct radeon_device *rdev); 356void r600_cp_stop(struct radeon_device *rdev); 357int r600_cp_start(struct radeon_device *rdev); 358void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); 359int r600_cp_resume(struct radeon_device *rdev); 360void r600_cp_fini(struct radeon_device *rdev); 361int r600_count_pipe_bits(uint32_t val); 362int r600_mc_wait_for_idle(struct radeon_device *rdev); 363int r600_pcie_gart_init(struct radeon_device *rdev); 364void r600_scratch_init(struct radeon_device *rdev); 365int r600_blit_init(struct radeon_device *rdev); 366void r600_blit_fini(struct radeon_device *rdev); 367int r600_init_microcode(struct radeon_device *rdev); 368void r600_fini_microcode(struct radeon_device *rdev); 369/* r600 irq */ 370irqreturn_t r600_irq_process(struct radeon_device *rdev); 371int r600_irq_init(struct radeon_device *rdev); 372void r600_irq_fini(struct radeon_device *rdev); 373void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 374int r600_irq_set(struct radeon_device *rdev); 375void r600_irq_suspend(struct radeon_device *rdev); 376void r600_disable_interrupts(struct radeon_device *rdev); 377void r600_rlc_stop(struct radeon_device *rdev); 378/* r600 audio */ 379int r600_audio_init(struct radeon_device *rdev); 380void r600_audio_set_clock(struct drm_encoder *encoder, int clock); 381struct r600_audio r600_audio_status(struct radeon_device *rdev); 382void r600_audio_fini(struct radeon_device *rdev); 383int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 384void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 385/* r600 blit */ 386int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages, 387 struct radeon_fence **fence, struct radeon_sa_bo **vb, 388 struct radeon_semaphore **sem); 389void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence, 390 struct radeon_sa_bo *vb, struct radeon_semaphore *sem); 391void r600_kms_blit_copy(struct radeon_device *rdev, 392 u64 src_gpu_addr, u64 dst_gpu_addr, 393 unsigned num_gpu_pages, 394 struct radeon_sa_bo *vb); 395uint64_t r600_get_gpu_clock(struct radeon_device *rdev); 396 397/* 398 * rv770,rv730,rv710,rv740 399 */ 400int rv770_init(struct radeon_device *rdev); 401void rv770_fini(struct radeon_device *rdev); 402int rv770_suspend(struct radeon_device *rdev); 403int rv770_resume(struct radeon_device *rdev); 404void rv770_pm_misc(struct radeon_device *rdev); 405u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 406void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 407void r700_cp_stop(struct radeon_device *rdev); 408void r700_cp_fini(struct radeon_device *rdev); 409int rv770_copy_dma(struct radeon_device *rdev, 410 uint64_t src_offset, uint64_t dst_offset, 411 unsigned num_gpu_pages, 412 struct radeon_fence **fence); 413 414/* 415 * evergreen 416 */ 417struct evergreen_mc_save { 418 u32 vga_render_control; 419 u32 vga_hdp_control; 420 bool crtc_enabled[RADEON_MAX_CRTCS]; 421}; 422 423void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); 424int evergreen_init(struct radeon_device *rdev); 425void evergreen_fini(struct radeon_device *rdev); 426int evergreen_suspend(struct radeon_device *rdev); 427int evergreen_resume(struct radeon_device *rdev); 428bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 429int evergreen_asic_reset(struct radeon_device *rdev); 430void evergreen_bandwidth_update(struct radeon_device *rdev); 431void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 432void evergreen_hpd_init(struct radeon_device *rdev); 433void evergreen_hpd_fini(struct radeon_device *rdev); 434bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 435void evergreen_hpd_set_polarity(struct radeon_device *rdev, 436 enum radeon_hpd_id hpd); 437u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); 438int evergreen_irq_set(struct radeon_device *rdev); 439irqreturn_t evergreen_irq_process(struct radeon_device *rdev); 440extern int evergreen_cs_parse(struct radeon_cs_parser *p); 441extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); 442extern void evergreen_pm_misc(struct radeon_device *rdev); 443extern void evergreen_pm_prepare(struct radeon_device *rdev); 444extern void evergreen_pm_finish(struct radeon_device *rdev); 445extern void sumo_pm_init_profile(struct radeon_device *rdev); 446extern void btc_pm_init_profile(struct radeon_device *rdev); 447extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); 448extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 449extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); 450extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); 451void evergreen_disable_interrupt_state(struct radeon_device *rdev); 452int evergreen_blit_init(struct radeon_device *rdev); 453int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 454void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, 455 struct radeon_fence *fence); 456void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, 457 struct radeon_ib *ib); 458int evergreen_copy_dma(struct radeon_device *rdev, 459 uint64_t src_offset, uint64_t dst_offset, 460 unsigned num_gpu_pages, 461 struct radeon_fence **fence); 462void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 463u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev); 464void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); 465void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); 466void evergreen_mc_program(struct radeon_device *rdev); 467int evergreen_mc_init(struct radeon_device *rdev); 468void evergreen_irq_suspend(struct radeon_device *rdev); 469 470/* 471 * cayman 472 */ 473void cayman_fence_ring_emit(struct radeon_device *rdev, 474 struct radeon_fence *fence); 475void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); 476int cayman_init(struct radeon_device *rdev); 477void cayman_fini(struct radeon_device *rdev); 478int cayman_suspend(struct radeon_device *rdev); 479int cayman_resume(struct radeon_device *rdev); 480int cayman_asic_reset(struct radeon_device *rdev); 481void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 482int cayman_vm_init(struct radeon_device *rdev); 483void cayman_vm_fini(struct radeon_device *rdev); 484void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 485uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); 486void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe, 487 uint64_t addr, unsigned count, 488 uint32_t incr, uint32_t flags); 489int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 490int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 491void cayman_dma_ring_ib_execute(struct radeon_device *rdev, 492 struct radeon_ib *ib); 493bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 494void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 495extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev, 496 int ring, u32 cp_int_cntl); 497 498/* DCE6 - SI */ 499void dce6_bandwidth_update(struct radeon_device *rdev); 500 501/* 502 * si 503 */ 504void si_fence_ring_emit(struct radeon_device *rdev, 505 struct radeon_fence *fence); 506void si_pcie_gart_tlb_flush(struct radeon_device *rdev); 507int si_init(struct radeon_device *rdev); 508void si_fini(struct radeon_device *rdev); 509int si_suspend(struct radeon_device *rdev); 510int si_resume(struct radeon_device *rdev); 511bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 512int si_asic_reset(struct radeon_device *rdev); 513void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 514int si_irq_set(struct radeon_device *rdev); 515irqreturn_t si_irq_process(struct radeon_device *rdev); 516int si_vm_init(struct radeon_device *rdev); 517void si_vm_fini(struct radeon_device *rdev); 518void si_vm_set_page(struct radeon_device *rdev, uint64_t pe, 519 uint64_t addr, unsigned count, 520 uint32_t incr, uint32_t flags); 521void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 522int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 523uint64_t si_get_gpu_clock(struct radeon_device *rdev); 524int si_copy_dma(struct radeon_device *rdev, 525 uint64_t src_offset, uint64_t dst_offset, 526 unsigned num_gpu_pages, 527 struct radeon_fence **fence); 528void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 529void si_rlc_fini(struct radeon_device *rdev); 530int si_rlc_init(struct radeon_device *rdev); 531 532#endif 533