Searched refs:instruction (Results 1 - 25 of 62) sorted by relevance

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/freebsd-11-stable/contrib/xz/src/liblzma/simple/
H A Dia64.c41 uint64_t instruction = 0; local
44 instruction += (uint64_t)(
48 uint64_t inst_norm = instruction >> bit_res;
73 instruction &= (1U << bit_res) - 1;
74 instruction |= (inst_norm << bit_res);
78 instruction
/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulationStateARM.h42 ReadPseudoMemory(lldb_private::EmulateInstruction *instruction, void *baton,
47 WritePseudoMemory(lldb_private::EmulateInstruction *instruction, void *baton,
51 static bool ReadPseudoRegister(lldb_private::EmulateInstruction *instruction,
57 WritePseudoRegister(lldb_private::EmulateInstruction *instruction,
H A DEmulationStateARM.cpp144 EmulateInstruction *instruction, void *baton,
185 EmulateInstruction *instruction, void *baton,
221 EmulateInstruction *instruction, void *baton,
240 EmulateInstruction *instruction, void *baton,
143 ReadPseudoMemory( EmulateInstruction *instruction, void *baton, const EmulateInstruction::Context &context, lldb::addr_t addr, void *dst, size_t length) argument
184 WritePseudoMemory( EmulateInstruction *instruction, void *baton, const EmulateInstruction::Context &context, lldb::addr_t addr, const void *dst, size_t length) argument
220 ReadPseudoRegister( EmulateInstruction *instruction, void *baton, const lldb_private::RegisterInfo *reg_info, lldb_private::RegisterValue &reg_value) argument
239 WritePseudoRegister( EmulateInstruction *instruction, void *baton, const EmulateInstruction::Context &context, const lldb_private::RegisterInfo *reg_info, const lldb_private::RegisterValue &reg_value) argument
/freebsd-11-stable/contrib/binutils/gas/config/
H A Dtc-arm.c259 instruction. (For backward compatibility, those instructions
262 - The IT instruction may appear, and if it does is validated
275 conditional affix except in the scope of an IT instruction. */
307 unsigned long instruction; member in struct:arm_it
312 unconditional versions of the instruction, or -1 if nothing is
316 /* Set to the opcode if the instruction needs relaxation.
317 Zero if the instruction is not relaxed. */
520 /* Parameters to instruction. */
526 /* Basic instruction code. */
529 /* Thumb-format instruction cod
17770 negate_data_op(unsigned long * instruction, unsigned long value) argument
17850 thumb32_negate_data_op(offsetT *instruction, unsigned int value) argument
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H A Dtc-score.c47 #define BAD_ARGS _("bad arguments to instruction")
49 #define BAD_COND _("instruction is not conditional")
53 #define ERR_FOR_SCORE5U_ATOMIC _("This architecture doesn't support atomic instruction")
56 #define BAD_GARBAGE _("garbage following instruction");
123 /* Default will do instruction relax, -O0 will set g_opt = 0. */
141 unsigned long instruction; member in struct:score_it
753 /* Macro instruction. */
871 inst.instruction |= reg << shift;
927 if ((((inst.instruction >> 15) & 0x10) == 0)
928 && (((inst.instruction >> 1
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H A Dtc-cr16.c36 /* Maximum size of a single instruction (in words). */
65 /* Current instruction we're assembling. */
66 const inst *instruction; variable
73 /* Array to hold an instruction encoding. */
79 /* A copy of the original instruction (used in error messages). */
445 /* Reset global variables before parsing a new instruction. */
614 /* 'opcode' points to the start of the instruction, whether
615 we need to change the instruction's fixed encoding. */
699 /* Apply a fixS (fixup of an instruction or data that we didn't have
799 /* Insert unique names into hash table. The CR16 instruction se
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/freebsd-11-stable/contrib/binutils/opcodes/
H A Dcr16-dis.c48 /* Structure to map valid 'cinv' instruction options. */
70 /* Number of valid 'cinv' instruction options. */
84 const inst *instruction; variable
85 /* Current instruction we're disassembling. */
87 /* The current instruction is read into 3 consecutive words. */
93 /* Nonzero means a IMM4 instruction. */
95 /* Nonzero means the instruction's original size is
126 /* Retrieve the number of operands for the current assembled instruction. */
133 for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++)
161 /* Given a 'CC' instruction constan
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H A Darc-dis.h53 unsigned char* instruction; member in struct:arcDisState
/freebsd-11-stable/contrib/llvm-project/lld/lib/ReaderWriter/MachO/
H A DArchHandler_arm.cpp181 static bool isThumbMovw(uint32_t instruction);
182 static bool isThumbMovt(uint32_t instruction);
183 static bool isArmMovw(uint32_t instruction);
184 static bool isArmMovt(uint32_t instruction);
185 static int32_t getDisplacementFromThumbBranch(uint32_t instruction, uint32_t);
186 static int32_t getDisplacementFromArmBranch(uint32_t instruction);
187 static uint16_t getWordFromThumbMov(uint32_t instruction);
188 static uint16_t getWordFromArmMov(uint32_t instruction);
194 static uint32_t setWordFromThumbMov(uint32_t instruction, uint16_t word);
195 static uint32_t setWordFromArmMov(uint32_t instruction, uint16_
356 getDisplacementFromArmBranch(uint32_t instruction) argument
368 setDisplacementInArmBranch(uint32_t instruction, int32_t displacement, bool targetIsThumb) argument
398 getDisplacementFromThumbBranch(uint32_t instruction, uint32_t instrAddr) argument
423 setDisplacementInThumbBranch(uint32_t instruction, uint32_t instrAddr, int32_t displacement, bool targetIsThumb) argument
462 isThumbMovw(uint32_t instruction) argument
466 isThumbMovt(uint32_t instruction) argument
470 isArmMovw(uint32_t instruction) argument
474 isArmMovt(uint32_t instruction) argument
478 getWordFromThumbMov(uint32_t instruction) argument
487 getWordFromArmMov(uint32_t instruction) argument
532 uint32_t instruction = *(const ulittle32_t *)fixupContent; local
791 uint32_t instruction = *(const ulittle32_t *)fixupContent; local
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H A DArchHandler_arm64.cpp341 uint32_t ArchHandler_arm64::setDisplacementInADRP(uint32_t instruction, argument
345 assert(((instruction & 0x9F000000) == 0x90000000) &&
346 "reloc not on ADRP instruction");
349 return (instruction & 0x9F00001F) | immlo | immhi;
353 ArchHandler_arm64::offset12KindFromInstruction(uint32_t instruction) { argument
354 if (instruction & 0x08000000) {
355 switch ((instruction >> 30) & 0x3) {
357 if ((instruction & 0x04800000) == 0x04800000)
371 uint32_t ArchHandler_arm64::setImm12(uint32_t instruction, uint32_t offset) { argument
374 return (instruction
595 uint32_t instruction; local
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/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/UnwindAssembly/InstEmulation/
H A DUnwindAssemblyInstEmulation.h80 ReadMemory(lldb_private::EmulateInstruction *instruction, void *baton,
85 WriteMemory(lldb_private::EmulateInstruction *instruction, void *baton,
89 static bool ReadRegister(lldb_private::EmulateInstruction *instruction,
95 WriteRegister(lldb_private::EmulateInstruction *instruction, void *baton,
101 // ReadMemory (lldb_private::EmulateInstruction *instruction,
107 size_t WriteMemory(lldb_private::EmulateInstruction *instruction,
111 bool ReadRegister(lldb_private::EmulateInstruction *instruction,
115 bool WriteRegister(lldb_private::EmulateInstruction *instruction,
141 // While processing the instruction stream, we need to communicate some state
147 // The instruction w
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H A DUnwindAssemblyInstEmulation.cpp59 // The instruction emulation subclass setup the unwind plan for the first
60 // instruction.
115 // Make a copy of the current instruction Row and save it in m_curr_row
127 // UnwindPlan uses) for quick reference during instruction parsing.
134 // instruction parsing.
140 // instruction.
162 // instruction.
187 // If the last instruction was conditional with a different
199 true; // The last instruction might already
225 // If the current instruction i
360 ReadMemory( EmulateInstruction *instruction, void *baton, const EmulateInstruction::Context &context, lldb::addr_t addr, void *dst, size_t dst_len) argument
379 WriteMemory( EmulateInstruction *instruction, void *baton, const EmulateInstruction::Context &context, lldb::addr_t addr, const void *dst, size_t dst_len) argument
389 WriteMemory( EmulateInstruction *instruction, const EmulateInstruction::Context &context, lldb::addr_t addr, const void *dst, size_t dst_len) argument
462 ReadRegister(EmulateInstruction *instruction, void *baton, const RegisterInfo *reg_info, RegisterValue &reg_value) argument
472 ReadRegister(EmulateInstruction *instruction, const RegisterInfo *reg_info, RegisterValue &reg_value) argument
491 WriteRegister( EmulateInstruction *instruction, void *baton, const EmulateInstruction::Context &context, const RegisterInfo *reg_info, const RegisterValue &reg_value) argument
500 WriteRegister( EmulateInstruction *instruction, const EmulateInstruction::Context &context, const RegisterInfo *reg_info, const RegisterValue &reg_value) argument
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/freebsd-11-stable/sys/dev/ncr/
H A Dlocate.pl10 Useful to find the failed NCR instruction ...
/freebsd-11-stable/contrib/binutils/include/opcode/
H A Dalpha.h72 /* A macro to extract the major opcode from an instruction. */
87 /* How far the operand is left shifted in the instruction. */
97 operand value into an instruction, check this field.
101 (i is the instruction which we are filling in, o is a pointer to
106 instruction and the operand value. It will return the new value
107 of the instruction. If the ERRMSG argument is not NULL, then if
112 unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
115 extract this operand type from an instruction, check this field.
122 (i is the instruction, o is a pointer to this structure, and op
126 instruction valu
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H A Dppc.h122 /* Opcode is an e500 SPE floating point instruction. */
149 /* A macro to extract the major opcode from an instruction. */
160 /* How far the operand is left shifted in the instruction.
166 operand value into an instruction, check this field.
170 (i is the instruction which we are filling in, o is a pointer to
174 instruction and the operand value. It will return the new value
175 of the instruction. If the ERRMSG argument is not NULL, then if
181 (unsigned long instruction, long op, int dialect, const char **errmsg);
184 extract this operand type from an instruction, check this field.
190 (i is the instruction,
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H A Dcr16.h157 /* CR16 instruction types. */
170 /* Maximum value supported for instruction types. */
172 /* Mask to record an instruction type. */
174 /* Return instruction type, given instruction's attributes. */
177 /* Indicates whether this instruction has a register list as parameter. */
184 /* Printing formats, where the instruction prefix isn't consecutive. */
192 /* Indicates whether this instruction can be relaxed. */
195 /* Indicates that instruction uses user registers (and not
206 /* Maximum operands per instruction
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/freebsd-11-stable/sys/dev/aic7xxx/aicasm/
H A Daicasm_insformat.h104 struct instruction { struct
108 STAILQ_ENTRY(instruction) links;
H A Daicasm.h88 struct instruction *seq_alloc(void);
H A Daicasm.c100 static STAILQ_HEAD(,instruction) seq_program;
323 struct instruction *cur_instr;
352 struct instruction *cur_instr;
525 struct instruction *cur_instr;
605 /* Don't count this instruction as it is in a patch
671 * one and wait for our instruction pointer to
735 struct instruction *
738 struct instruction *new_instr;
740 new_instr = (struct instruction *)malloc(sizeof(struct instruction));
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/freebsd-11-stable/contrib/llvm-project/lldb/include/lldb/Core/
H A DEmulateInstruction.h51 /// Objects can be asked to read an instruction which will cause a call to the
56 /// instruction.
59 /// registers/memory to actually emulate the instruction on a real or virtual
91 /// the instruction is just a bonus.
101 // Read an instruction opcode from memory
323 void Dump(Stream &s, EmulateInstruction *instruction) const;
326 typedef size_t (*ReadMemoryCallback)(EmulateInstruction *instruction,
331 typedef size_t (*WriteMemoryCallback)(EmulateInstruction *instruction,
336 typedef bool (*ReadRegisterCallback)(EmulateInstruction *instruction,
341 typedef bool (*WriteRegisterCallback)(EmulateInstruction *instruction,
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/freebsd-11-stable/contrib/subversion/subversion/libsvn_fs_x/
H A Dreps.c61 * - reference other instruction and specify how many of instructions of
68 * instruction and the number of instructions to execute.
76 /* A single instruction. The instruction type is being encoded in OFFSET.
82 * reference to instruction sub-sequence starting with
443 instruction_t instruction; local
450 /* new instruction */
451 instruction.offset = (apr_int32_t)builder->text->len;
452 instruction.count = (apr_uint32_t)len;
453 APR_ARRAY_PUSH(builder->instructions, instruction_t) = instruction;
530 instruction_t instruction; local
602 const instruction_t *instruction; local
753 const instruction_t *instruction local
828 instruction_t *instruction = instructions + i; local
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/freebsd-11-stable/contrib/llvm-project/lldb/bindings/interface/
H A DSBInstructionList.i17 SBInstructionList supports instruction (SBInstruction instance) iteration.
79 '''Access len of the instruction list.'''
83 '''Access instructions by integer index for array access or by lldb.SBAddress to find an instruction that matches a section offset address object.'''
85 # Find an instruction by index
89 # Find an instruction using a lldb.SBAddress object
/freebsd-11-stable/contrib/llvm-project/lldb/source/Core/
H A DEmulateInstruction.cpp248 size_t EmulateInstruction::ReadMemoryFrame(EmulateInstruction *instruction, argument
265 size_t EmulateInstruction::WriteMemoryFrame(EmulateInstruction *instruction, argument
283 bool EmulateInstruction::ReadRegisterFrame(EmulateInstruction *instruction, argument
294 bool EmulateInstruction::WriteRegisterFrame(EmulateInstruction *instruction, argument
305 size_t EmulateInstruction::ReadMemoryDefault(EmulateInstruction *instruction, argument
314 context.Dump(strm, instruction);
320 size_t EmulateInstruction::WriteMemoryDefault(EmulateInstruction *instruction, argument
329 context.Dump(strm, instruction);
334 bool EmulateInstruction::ReadRegisterDefault(EmulateInstruction *instruction, argument
350 bool EmulateInstruction::WriteRegisterDefault(EmulateInstruction *instruction, argument
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/freebsd-11-stable/sys/mips/rmi/dev/sec/
H A Drmilib.c151 desc->ctl_desc.instruction = 0;
1008 SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_BYPASS);
1013 SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_DES);
1017 SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_3DES);
1022 SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_AES128);
1027 SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_AES192);
1032 SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_AES256);
1036 SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_ARC4);
1037 SET_FIELD(ctl_desc->instruction, CTL_DSC_ARC4_KEYLEN,
1039 SET_FIELD(ctl_desc->instruction, CTL_DSC_ARC4_LOADSTAT
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Support/Unix/
H A DMemory.inc149 // Rely on protectMappedMemory to invalidate instruction cache.
189 // Certain ARM implementations treat icache clear instruction as a memory read,
191 // to temporarily add PROT_READ for the sake of flushing the instruction caches.
214 /// that has been emitted it must invalidate the instruction cache on some
231 assert(Status == ZX_OK && "cannot invalidate instruction cache");

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