133965Sjdp/* alpha.h -- Header file for Alpha opcode table 2130561Sobrien Copyright 1996, 1999, 2001, 2003 Free Software Foundation, Inc. 333965Sjdp Contributed by Richard Henderson <rth@tamu.edu>, 433965Sjdp patterned after the PPC opcode table written by Ian Lance Taylor. 533965Sjdp 633965SjdpThis file is part of GDB, GAS, and the GNU binutils. 733965Sjdp 833965SjdpGDB, GAS, and the GNU binutils are free software; you can redistribute 933965Sjdpthem and/or modify them under the terms of the GNU General Public 1033965SjdpLicense as published by the Free Software Foundation; either version 1133965Sjdp1, or (at your option) any later version. 1233965Sjdp 1333965SjdpGDB, GAS, and the GNU binutils are distributed in the hope that they 1433965Sjdpwill be useful, but WITHOUT ANY WARRANTY; without even the implied 1533965Sjdpwarranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 1633965Sjdpthe GNU General Public License for more details. 1733965Sjdp 1833965SjdpYou should have received a copy of the GNU General Public License 1933965Sjdpalong with this file; see the file COPYING. If not, write to the Free 20218822SdimSoftware Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 2133965Sjdp 2233965Sjdp#ifndef OPCODE_ALPHA_H 2333965Sjdp#define OPCODE_ALPHA_H 2433965Sjdp 2533965Sjdp/* The opcode table is an array of struct alpha_opcode. */ 2633965Sjdp 2733965Sjdpstruct alpha_opcode 2833965Sjdp{ 2933965Sjdp /* The opcode name. */ 3033965Sjdp const char *name; 3133965Sjdp 3233965Sjdp /* The opcode itself. Those bits which will be filled in with 3333965Sjdp operands are zeroes. */ 3433965Sjdp unsigned opcode; 3533965Sjdp 3633965Sjdp /* The opcode mask. This is used by the disassembler. This is a 3733965Sjdp mask containing ones indicating those bits which must match the 3833965Sjdp opcode field, and zeroes indicating those bits which need not 3933965Sjdp match (and are presumably filled in by operands). */ 4033965Sjdp unsigned mask; 4133965Sjdp 4233965Sjdp /* One bit flags for the opcode. These are primarily used to 4333965Sjdp indicate specific processors and environments support the 4433965Sjdp instructions. The defined values are listed below. */ 4533965Sjdp unsigned flags; 4633965Sjdp 4733965Sjdp /* An array of operand codes. Each code is an index into the 4833965Sjdp operand table. They appear in the order which the operands must 4933965Sjdp appear in assembly code, and are terminated by a zero. */ 5033965Sjdp unsigned char operands[4]; 5133965Sjdp}; 5233965Sjdp 5333965Sjdp/* The table itself is sorted by major opcode number, and is otherwise 5433965Sjdp in the order in which the disassembler should consider 5533965Sjdp instructions. */ 5633965Sjdpextern const struct alpha_opcode alpha_opcodes[]; 5760484Sobrienextern const unsigned alpha_num_opcodes; 5833965Sjdp 5933965Sjdp/* Values defined for the flags field of a struct alpha_opcode. */ 6033965Sjdp 6133965Sjdp/* CPU Availability */ 6233965Sjdp#define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */ 6333965Sjdp#define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */ 6433965Sjdp#define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */ 6560484Sobrien#define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */ 6633965Sjdp#define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */ 6733965Sjdp#define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */ 6833965Sjdp#define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */ 6933965Sjdp 7060484Sobrien#define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6)) 7133965Sjdp 7233965Sjdp/* A macro to extract the major opcode from an instruction. */ 7333965Sjdp#define AXP_OP(i) (((i) >> 26) & 0x3F) 7433965Sjdp 7533965Sjdp/* The total number of major opcodes. */ 7633965Sjdp#define AXP_NOPS 0x40 7733965Sjdp 7833965Sjdp 7933965Sjdp/* The operands table is an array of struct alpha_operand. */ 8033965Sjdp 8133965Sjdpstruct alpha_operand 8233965Sjdp{ 8333965Sjdp /* The number of bits in the operand. */ 8489857Sobrien unsigned int bits : 5; 8533965Sjdp 8633965Sjdp /* How far the operand is left shifted in the instruction. */ 8789857Sobrien unsigned int shift : 5; 8833965Sjdp 8933965Sjdp /* The default relocation type for this operand. */ 9089857Sobrien signed int default_reloc : 16; 9133965Sjdp 9233965Sjdp /* One bit syntax flags. */ 9389857Sobrien unsigned int flags : 16; 9433965Sjdp 9533965Sjdp /* Insertion function. This is used by the assembler. To insert an 9633965Sjdp operand value into an instruction, check this field. 9733965Sjdp 9833965Sjdp If it is NULL, execute 9933965Sjdp i |= (op & ((1 << o->bits) - 1)) << o->shift; 10033965Sjdp (i is the instruction which we are filling in, o is a pointer to 10133965Sjdp this structure, and op is the opcode value; this assumes twos 10233965Sjdp complement arithmetic). 10333965Sjdp 10433965Sjdp If this field is not NULL, then simply call it with the 10533965Sjdp instruction and the operand value. It will return the new value 10633965Sjdp of the instruction. If the ERRMSG argument is not NULL, then if 10733965Sjdp the operand value is illegal, *ERRMSG will be set to a warning 10833965Sjdp string (the operand will be inserted in any case). If the 10933965Sjdp operand value is legal, *ERRMSG will be unchanged (most operands 11033965Sjdp can accept any value). */ 111130561Sobrien unsigned (*insert) (unsigned instruction, int op, const char **errmsg); 11233965Sjdp 11333965Sjdp /* Extraction function. This is used by the disassembler. To 11433965Sjdp extract this operand type from an instruction, check this field. 11533965Sjdp 11633965Sjdp If it is NULL, compute 11733965Sjdp op = ((i) >> o->shift) & ((1 << o->bits) - 1); 11833965Sjdp if ((o->flags & AXP_OPERAND_SIGNED) != 0 11933965Sjdp && (op & (1 << (o->bits - 1))) != 0) 12033965Sjdp op -= 1 << o->bits; 12133965Sjdp (i is the instruction, o is a pointer to this structure, and op 12233965Sjdp is the result; this assumes twos complement arithmetic). 12333965Sjdp 12433965Sjdp If this field is not NULL, then simply call it with the 12533965Sjdp instruction value. It will return the value of the operand. If 12633965Sjdp the INVALID argument is not NULL, *INVALID will be set to 12733965Sjdp non-zero if this operand type can not actually be extracted from 12833965Sjdp this operand (i.e., the instruction does not match). If the 12933965Sjdp operand is valid, *INVALID will not be changed. */ 130130561Sobrien int (*extract) (unsigned instruction, int *invalid); 13133965Sjdp}; 13233965Sjdp 13333965Sjdp/* Elements in the table are retrieved by indexing with values from 13433965Sjdp the operands field of the alpha_opcodes table. */ 13533965Sjdp 13633965Sjdpextern const struct alpha_operand alpha_operands[]; 13760484Sobrienextern const unsigned alpha_num_operands; 13833965Sjdp 13933965Sjdp/* Values defined for the flags field of a struct alpha_operand. */ 14033965Sjdp 14133965Sjdp/* Mask for selecting the type for typecheck purposes */ 14233965Sjdp#define AXP_OPERAND_TYPECHECK_MASK \ 14333965Sjdp (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR | \ 14433965Sjdp AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | \ 14533965Sjdp AXP_OPERAND_UNSIGNED) 14633965Sjdp 14733965Sjdp/* This operand does not actually exist in the assembler input. This 14833965Sjdp is used to support extended mnemonics, for which two operands fields 14933965Sjdp are identical. The assembler should call the insert function with 15033965Sjdp any op value. The disassembler should call the extract function, 15133965Sjdp ignore the return value, and check the value placed in the invalid 15233965Sjdp argument. */ 15333965Sjdp#define AXP_OPERAND_FAKE 01 15433965Sjdp 15533965Sjdp/* The operand should be wrapped in parentheses rather than separated 15633965Sjdp from the previous by a comma. This is used for the load and store 15733965Sjdp instructions which want their operands to look like "Ra,disp(Rb)". */ 15833965Sjdp#define AXP_OPERAND_PARENS 02 15933965Sjdp 16033965Sjdp/* Used in combination with PARENS, this supresses the supression of 16133965Sjdp the comma. This is used for "jmp Ra,(Rb),hint". */ 16233965Sjdp#define AXP_OPERAND_COMMA 04 16333965Sjdp 16433965Sjdp/* This operand names an integer register. */ 16533965Sjdp#define AXP_OPERAND_IR 010 16633965Sjdp 16733965Sjdp/* This operand names a floating point register. */ 16833965Sjdp#define AXP_OPERAND_FPR 020 16933965Sjdp 17033965Sjdp/* This operand is a relative branch displacement. The disassembler 17133965Sjdp prints these symbolically if possible. */ 17233965Sjdp#define AXP_OPERAND_RELATIVE 040 17333965Sjdp 17433965Sjdp/* This operand takes signed values. */ 17533965Sjdp#define AXP_OPERAND_SIGNED 0100 17633965Sjdp 17733965Sjdp/* This operand takes unsigned values. This exists primarily so that 17833965Sjdp a flags value of 0 can be treated as end-of-arguments. */ 17933965Sjdp#define AXP_OPERAND_UNSIGNED 0200 18033965Sjdp 18133965Sjdp/* Supress overflow detection on this field. This is used for hints. */ 18233965Sjdp#define AXP_OPERAND_NOOVERFLOW 0400 18333965Sjdp 18433965Sjdp/* Mask for optional argument default value. */ 18533965Sjdp#define AXP_OPERAND_OPTIONAL_MASK 07000 18633965Sjdp 18733965Sjdp/* This operand defaults to zero. This is used for jump hints. */ 18833965Sjdp#define AXP_OPERAND_DEFAULT_ZERO 01000 18933965Sjdp 19033965Sjdp/* This operand should default to the first (real) operand and is used 19133965Sjdp in conjunction with AXP_OPERAND_OPTIONAL. This allows 19233965Sjdp "and $0,3,$0" to be written as "and $0,3", etc. I don't like 19333965Sjdp it, but it's what DEC does. */ 19433965Sjdp#define AXP_OPERAND_DEFAULT_FIRST 02000 19533965Sjdp 19633965Sjdp/* Similarly, this operand should default to the second (real) operand. 19733965Sjdp This allows "negl $0" instead of "negl $0,$0". */ 19833965Sjdp#define AXP_OPERAND_DEFAULT_SECOND 04000 19933965Sjdp 20033965Sjdp 20133965Sjdp/* Register common names */ 20233965Sjdp 20333965Sjdp#define AXP_REG_V0 0 20433965Sjdp#define AXP_REG_T0 1 20533965Sjdp#define AXP_REG_T1 2 20633965Sjdp#define AXP_REG_T2 3 20733965Sjdp#define AXP_REG_T3 4 20833965Sjdp#define AXP_REG_T4 5 20933965Sjdp#define AXP_REG_T5 6 21033965Sjdp#define AXP_REG_T6 7 21133965Sjdp#define AXP_REG_T7 8 21233965Sjdp#define AXP_REG_S0 9 21333965Sjdp#define AXP_REG_S1 10 21433965Sjdp#define AXP_REG_S2 11 21533965Sjdp#define AXP_REG_S3 12 21633965Sjdp#define AXP_REG_S4 13 21733965Sjdp#define AXP_REG_S5 14 21833965Sjdp#define AXP_REG_FP 15 21933965Sjdp#define AXP_REG_A0 16 22033965Sjdp#define AXP_REG_A1 17 22133965Sjdp#define AXP_REG_A2 18 22233965Sjdp#define AXP_REG_A3 19 22333965Sjdp#define AXP_REG_A4 20 22433965Sjdp#define AXP_REG_A5 21 22533965Sjdp#define AXP_REG_T8 22 22633965Sjdp#define AXP_REG_T9 23 22733965Sjdp#define AXP_REG_T10 24 22833965Sjdp#define AXP_REG_T11 25 22933965Sjdp#define AXP_REG_RA 26 23033965Sjdp#define AXP_REG_PV 27 23133965Sjdp#define AXP_REG_T12 27 23233965Sjdp#define AXP_REG_AT 28 23333965Sjdp#define AXP_REG_GP 29 23433965Sjdp#define AXP_REG_SP 30 23533965Sjdp#define AXP_REG_ZERO 31 23633965Sjdp 23733965Sjdp#endif /* OPCODE_ALPHA_H */ 238