Searched refs:getRegClass (Results 1 - 25 of 185) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsOptionRecord.h47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID));
48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID));
49 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID));
50 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID));
51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
52 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID));
53 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID));
54 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID));
55 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBank.cpp34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
104 const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
H A DInstructionSelect.cpp174 auto SrcRC = MRI.getRegClass(SrcReg);
175 auto DstRC = MRI.getRegClass(DstReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DAllocationOrder.cpp36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
H A DRegAllocBase.cpp107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg))
137 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
H A DTargetRegisterInfo.cpp157 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
179 const TargetRegisterClass *SubRC = getRegClass(It.getID());
244 return TRI->getRegClass(I + countTrailingZeros(Common));
488 RC = MRI.getRegClass(Reg);
H A DPeepholeOptimizer.cpp474 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
485 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr;
571 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
669 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
731 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg);
761 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg);
1232 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg);
1425 if (MRI->getRegClass(DstReg) != MRI->getRegClass(PrevDstReg))
1960 if (MRI.getRegClass(MODe
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H A DMachineLoopUtils.cpp56 R = MRI.createVirtualRegister(MRI.getRegClass(OrigR));
68 MRI.constrainRegClass(R, MRI.getRegClass(Use->getReg()));
H A DLiveRangeShrink.cpp193 MRI.getRegClass(DefMO->getReg()) ==
194 MRI.getRegClass(MO.getReg())) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp66 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
170 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg))
H A DWebAssemblyMemIntrinsicResults.cpp171 if (MRI.getRegClass(FromReg) != MRI.getRegClass(ToReg))
H A DWebAssemblyRegColoring.cpp140 const TargetRegisterClass *RC = MRI->getRegClass(Old);
145 if (MRI->getRegClass(SortedIntervals[C]->reg) != RC)
H A DWebAssemblyInstrInfo.cpp65 ? MRI.getRegClass(DestReg)
197 bool IsBrOnExn = Cond[1].isReg() && MRI.getRegClass(Cond[1].getReg()) ==
228 MRI.getRegClass(Cond[1].getReg()) == &WebAssembly::EXNREFRegClass)
H A DWebAssemblyExplicitLocals.cpp243 const TargetRegisterClass *RC = MRI.getRegClass(OldReg);
278 const TargetRegisterClass *RC = MRI.getRegClass(OldReg);
353 const TargetRegisterClass *RC = MRI.getRegClass(OldReg);
384 typeForRegClass(MRI.getRegClass(Reg)));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterBankInfo.cpp149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) &&
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&
161 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) &&
163 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPREven_and_tGPR_and_tcGPRRegClassID)) &&
165 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) &&
H A DA15SDOptimizer.cpp139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
271 MRI->getRegClass(MI->getOperand(1).getReg());
272 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
517 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
518 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
534 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
540 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
641 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp132 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) !=
133 MRI.getRegClass(AddendSrcReg))
138 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg())
238 MRI.getRegClass(OldFMAReg)))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h135 return isSGPRClass(getRegClass(RCID));
141 RC = MRI.getRegClass(Reg);
282 const TargetRegisterClass *getRegClass(unsigned RCID) const;
H A DSIFixupVectorISel.cpp127 IdxRC = MRI.getRegClass(MI->getOperand(1).getReg());
137 BaseRC = MRI.getRegClass(BaseReg);
143 if (!TRI->hasVGPRs(MRI.getRegClass(IndexReg)))
H A DSIFixSGPRCopies.cpp161 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg())))
175 ? MRI.getRegClass(SrcReg)
182 ? MRI.getRegClass(DstReg)
223 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg)));
247 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg)))
292 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
677 DstRC = MRI->getRegClass(MI.getOperand(0).getReg());
678 Src0RC = MRI->getRegClass(MI.getOperand(1).getReg());
679 Src1RC = MRI->getRegClass(MI.getOperand(2).getReg());
787 const TargetRegisterClass *UseRC = MRI->getRegClass(Us
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&
118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
161 DstRC = MRI->getRegClass(VRBase);
204 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
233 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
314 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
379 II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
451 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
517 TRC == MRI->getRegClass(SrcReg)) {
574 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
615 TRI->getAllocatableClass(TRI->getRegClass(DstRCId
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp32 const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
122 MRI->getRegClass(VirtReg));
136 if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
171 if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp127 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
128 const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg,
169 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { function in class:X86InstructionSelector
197 X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg, function in class:X86InstructionSelector
200 return getRegClass(Ty, RegBank);
248 getRegClass(MRI.getType(SrcReg), SrcRegBank);
278 getRegClass(MRI.getType(DstReg), DstRegBank);
727 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
728 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
809 const TargetRegisterClass *DstRC = getRegClass(DstT
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp37 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
38 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);

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