Searched refs:dl (Results 1 - 25 of 300) sorted by last modified time

1234567891011>>

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1963 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1988 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1993 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1999 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2002 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2003 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2004 DAG.getConstant(0, dl, MVT::i32));
2007 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2011 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2016 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MV
1961 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn, SDValue ThisVal) const argument
2042 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, const SDLoc &dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument
2056 PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, SDValue &StackPtr, SmallVectorImpl<SDValue> &MemOpChains, ISD::ArgFlagsTy Flags) const argument
2089 SDLoc &dl = CLI.DL; local
2757 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, SelectionDAG &DAG) const argument
3352 promoteToConstantPool(const ARMTargetLowering *TLI, const GlobalValue *GV, SelectionDAG &DAG, EVT PtrVT, const SDLoc &dl) argument
3912 StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl, SDValue &Chain, const Value *OrigArg, unsigned InRegsParamRecordIdx, int ArgOffset, unsigned ArgSize) const argument
3966 VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl, SDValue &Chain, unsigned ArgOffset, unsigned TotalArgRegsSaveSize, bool ForceMutable) const argument
3986 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
4357 getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl, bool Signaling) const argument
4698 getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal, SDValue ARMcc, SDValue CCR, SDValue Cmp, SelectionDAG &DAG) const argument
5835 getZeroVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) argument
6426 isVMOVModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, const SDLoc &dl, EVT &VT, bool is128Bits, VMOVModImmType type) argument
7071 IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, const ARMSubtarget *ST, const SDLoc &dl) argument
7671 GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl) argument
7780 PromoteMVEPredVector(SDLoc dl, SDValue Pred, EVT VT, SelectionDAG &DAG) argument
8645 LowerSDIV_v4i8(SDValue X, SDValue Y, const SDLoc &dl, SelectionDAG &DAG) argument
8676 LowerSDIV_v4i16(SDValue N0, SDValue N1, const SDLoc &dl, SelectionDAG &DAG) argument
9489 DebugLoc dl = MI.getDebugLoc(); local
9613 DebugLoc dl = MI.getDebugLoc(); local
10072 emitPostLd(MachineBasicBlock *BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo *TII, const DebugLoc &dl, unsigned LdSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2) argument
10113 emitPostSt(MachineBasicBlock *BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo *TII, const DebugLoc &dl, unsigned StSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2) argument
10167 DebugLoc dl = MI.getDebugLoc(); local
10547 DebugLoc dl = MI.getDebugLoc(); local
[all...]
/freebsd-11-stable/contrib/sqlite3/
H A Dconfigure13494 for ac_lib in '' dl; do
/freebsd-11-stable/contrib/unbound/
H A Dconfigure17250 for ac_lib in '' dl; do
18255 for ac_lib in '' dl; do
/freebsd-11-stable/contrib/unbound/validator/
H A Dval_anchor.c353 * @param dl: length of dname.
358 size_t dl)
362 sldns_wirerr_get_type(rr, rl, dl),
363 sldns_wirerr_get_class(rr, rl, dl),
364 sldns_wirerr_get_rdatawl(rr, rl, dl),
365 sldns_wirerr_get_rdatalen(rr, rl, dl)+2))) {
369 rr, sldns_wirerr_get_type(rr, rl, dl),
370 sldns_wirerr_get_class(rr, rl, dl));
357 anchor_store_new_rr(struct val_anchors* anchors, uint8_t* rr, size_t rl, size_t dl) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp132 static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
2432 // FIXME dl should come from parent load or store, not from address
2433 SDLoc dl(N);
2442 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2481 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2493 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
2506 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
2508 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
2511 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2516 Disp = DAG.getTargetConstant(0, dl, getPointerT
2750 getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const argument
3470 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3488 LowerFormalArguments_32SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3759 LowerFormalArguments_64SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
4171 LowerFormalArguments_Darwin( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
4845 StoreTailCallArgumentsToStackSlot( SelectionDAG &DAG, SDValue Chain, const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs, SmallVectorImpl<SDValue> &MemOpChains, const SDLoc &dl) argument
4862 EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain, SDValue OldRetAddr, SDValue OldFP, int SPDiff, const SDLoc &dl) argument
4943 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) argument
4954 LowerMemOpCallTo( SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains, SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, const SDLoc &dl) argument
4978 PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) argument
5015 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
5147 transformCallee(const SDValue &Callee, SelectionDAG &DAG, const SDLoc &dl, const PPCSubtarget &Subtarget) argument
5259 prepareIndirectCall(SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, const SDLoc &dl) argument
5270 prepareDescriptorIndirectCall(SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, SDValue CallSeqStart, ImmutableCallSite CS, const SDLoc &dl, bool hasNest, const PPCSubtarget &Subtarget) argument
5363 buildCallOperands(SmallVectorImpl<SDValue> &Ops, CallingConv::ID CallConv, const SDLoc &dl, bool isTailCall, bool isVarArg, bool isPatchPoint, bool hasNest, SelectionDAG &DAG, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff, const PPCSubtarget &Subtarget, bool isIndirect) argument
5442 FinishCall( CallingConv::ID CallConv, const SDLoc &dl, bool isTailCall, bool isVarArg, bool isPatchPoint, bool hasNest, SelectionDAG &DAG, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue, SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff, unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const argument
5511 SDLoc &dl = CLI.DL; local
5583 LowerCall_32SVR4( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, bool isPatchPoint, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const argument
5836 LowerCall_64SVR4( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, bool isPatchPoint, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const argument
6497 LowerCall_Darwin( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, bool isPatchPoint, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const argument
6987 truncateScalarIntegerArg(ISD::ArgFlagsTy Flags, EVT ValVT, SelectionDAG &DAG, SDValue ArgValue, MVT LocVT, const SDLoc &dl) argument
7003 LowerFormalArguments_AIX( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
7079 LowerCall_AIX( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, bool isPatchPoint, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const argument
7247 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, SelectionDAG &DAG) const argument
7993 widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl) argument
8473 BuildSplatI(int Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, const SDLoc &dl) argument
8493 BuildIntrinsicOp(unsigned IID, SDValue Op, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT = MVT::Other) argument
8502 BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT = MVT::Other) argument
8512 BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, SDValue Op2, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT = MVT::Other) argument
8522 BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, const SDLoc &dl) argument
8930 GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl) argument
10687 DebugLoc dl = MI.getDebugLoc(); local
10791 DebugLoc dl = MI.getDebugLoc(); local
11247 DebugLoc dl = MI.getDebugLoc(); local
11287 DebugLoc dl = MI.getDebugLoc(); local
11355 DebugLoc dl = MI.getDebugLoc(); local
11523 DebugLoc dl = MI.getDebugLoc(); local
11602 DebugLoc dl = MI.getDebugLoc(); local
11781 DebugLoc dl = MI.getDebugLoc(); local
11836 DebugLoc dl = MI.getDebugLoc(); local
11858 DebugLoc dl = MI.getDebugLoc(); local
[all...]
H A DPPCInstrInfo.cpp794 const DebugLoc &dl, unsigned DestReg,
868 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
872 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
792 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &dl, unsigned DestReg, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg) const argument
H A DPPCISelLowering.h1012 SelectionDAG &DAG, const SDLoc &dl) const;
1014 const SDLoc &dl) const;
1018 const SDLoc &dl) const;
1021 const SDLoc &dl) const;
1048 const SDLoc &dl) const;
1050 SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const;
1074 const SDLoc &dl) const;
1101 const SDLoc &dl, SelectionDAG &DAG,
1103 SDValue FinishCall(CallingConv::ID CallConv, const SDLoc &dl,
1116 const SDLoc &dl, SelectionDA
[all...]
/freebsd-11-stable/contrib/elftoolchain/elfcopy/
H A Dsegments.c108 uint64_t dl, vma, lma, start, end; local
234 dl = s->vma - vma;
237 s0->vma -= dl;
247 s0->off += dl;
261 dl = vma - s->vma;
271 s0->vma += dl;
277 s0->off += dl;
381 dl = s->lma - lma;
384 s0->lma -= dl;
398 dl
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp102 static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl, argument
106 DiagnosticInfoUnsupported(MF.getFunction(), Msg, dl.getDebugLoc()));
2642 const SDLoc &dl, SelectionDAG &DAG) const {
2663 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2681 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2683 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2686 ValToCopy = lowerMasksToReg(ValToCopy, VA.getLocVT(), dl, DAG);
2688 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2699 errorUnsupported(DAG, dl, "SSE register return with SSE disabled");
2706 errorUnsupported(DAG, dl, "SSE
2638 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, SelectionDAG &DAG) const argument
2991 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, uint32_t *RegMask) const argument
3131 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) argument
3188 LowerMemArgument(SDValue Chain, CallingConv::ID CallConv, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, const CCValAssign &VA, MachineFrameInfo &MFI, unsigned i) const argument
[all...]
H A DX86InstrInfo.cpp5620 SDLoc dl(N);
5655 Load = DAG.getMachineNode(Opc, dl, VT, MVT::Other, AddrOps);
5701 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
5720 dl, MVT::Other, AddrOps);
H A DX86ISelLowering.h1274 SDValue expandIndirectJTBranch(const SDLoc& dl, SDValue Value,
1306 const SDLoc &dl, SelectionDAG &DAG,
1311 const SDLoc &dl, SelectionDAG &DAG,
1315 const SDLoc &dl, SelectionDAG &DAG,
1336 const SDLoc &dl) const;
1400 const SDLoc &dl, SelectionDAG &DAG,
1408 const SDLoc &dl, SelectionDAG &DAG) const override;
1512 const SDLoc &dl, SelectionDAG &DAG,
1543 X86StoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, argument
1546 :MemSDNode(Opcode, Order, dl, VT
1561 X86MaskedStoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
1579 TruncSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
1591 TruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
1603 MaskedTruncSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
1616 MaskedTruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
1631 X86MaskedGatherScatterSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
1649 X86MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
1663 X86MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO) argument
[all...]
H A DX86ISelDAGToDAG.cpp522 const SDLoc &dl, MVT VT, SDNode *Node);
524 const SDLoc &dl, MVT VT, SDNode *Node,
924 SDLoc dl(N);
928 Res = CurDAG->getNode(X86ISD::STRICT_VRNDSCALE, dl,
931 CurDAG->getTargetConstant(Imm, dl, MVT::i8)});
933 Res = CurDAG->getNode(X86ISD::VRNDSCALE, dl, N->getValueType(0),
935 CurDAG->getTargetConstant(Imm, dl, MVT::i8));
953 SDLoc dl(N);
954 SDValue Op0 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT,
956 SDValue Op1 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecV
3635 emitPCMPISTR(unsigned ROpc, unsigned MOpc, bool MayFoldLoad, const SDLoc &dl, MVT VT, SDNode *Node) argument
3667 emitPCMPESTR(unsigned ROpc, unsigned MOpc, bool MayFoldLoad, const SDLoc &dl, MVT VT, SDNode *Node, SDValue &InFlag) argument
[all...]
/freebsd-11-stable/contrib/unbound/contrib/android/
H A Dinstall_ndk.sh19 if ! curl -L -k -s -o "$HOME/android-sdk.zip" https://dl.google.com/android/repository/commandlinetools-linux-6200805_latest.zip;
26 if ! curl -L -k -s -o "$HOME/android-ndk.zip" https://dl.google.com/android/repository/android-ndk-r20b-linux-x86_64.zip;
/freebsd-11-stable/libexec/rtld-elf/
H A Drtld.c1860 uint32_t dl; local
1886 dl = hdr.strtab;
1887 if (dl + hdr.dirlist < dl)
1889 dl += hdr.dirlist;
1890 if (dl + hdr.dirlistlen < dl)
1892 dl += hdr.dirlistlen;
1893 if (dl > hint_stat.st_size)
/freebsd-11-stable/usr.sbin/rrenumd/
H A Dparser.y87 struct dst_list *dl;
111 %type <dl> dest_addrs dest_addr sin sin6
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp129 const SDLoc &dl,
168 CLI.setDebugLoc(dl)
286 const SDLoc &dl, const SDValue OldLHS,
289 return softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, dl, OldLHS,
296 const SDLoc &dl, const SDValue OldLHS,
402 auto Call = makeLibCall(DAG, LC1, RetVT, Ops, CallOptions, dl, Chain);
404 NewRHS = DAG.getConstant(0, dl, RetVT);
418 SDValue Tmp = DAG.getSetCC(dl, SetCCVT, NewLHS, NewRHS, CCCode);
419 auto Call2 = makeLibCall(DAG, LC2, RetVT, Ops, CallOptions, dl, Chain);
423 NewLHS = DAG.getSetCC(dl, SetCCV
126 makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef<SDValue> Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue InChain) const argument
283 softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &dl, const SDValue OldLHS, const SDValue OldRHS) const argument
293 softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &dl, const SDValue OldLHS, const SDValue OldRHS, SDValue &Chain, bool IsSignaling) const argument
4635 BuildExactSDIV(const TargetLowering &TLI, SDNode *N, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDNode *> &Created) argument
[all...]
H A DLegalizeIntegerTypes.cpp305 SDLoc dl(N);
313 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
317 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
321 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp));
330 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
345 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
349 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
359 DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
367 Res = DAG.getNode(ISD::SRL, dl, NOutVT, Res,
368 DAG.getConstant(ShiftAmt, dl, ShiftAmtT
3815 IntegerExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &dl) argument
4019 SDLoc dl = SDLoc(N); local
[all...]
H A DDAGCombiner.cpp7397 SDLoc dl(N);
7419 return DAG.getNode(N->getOpcode(), dl, VT, N0,
7420 DAG.getConstant(RotAmt, dl, N1.getValueType()));
7428 return DAG.getNode(N->getOpcode(), dl, VT, N0, NewOp1);
7441 DAG.FoldConstantArithmetic(CombineOp, dl, ShiftVT, C1, C2)) {
7442 SDValue BitsizeC = DAG.getConstant(Bitsize, dl, ShiftVT);
7444 ISD::SREM, dl, ShiftVT, CombinedShift.getNode(),
7446 return DAG.getNode(N->getOpcode(), dl, VT, N0->getOperand(0),
9563 SDLoc dl(Ld);
9564 SDValue PassThru = DAG.getNode(ExtOpc, dl, V
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DBranchFolding.cpp470 DebugLoc dl = CurMBB->findBranchDebugLoc(); local
476 TII->insertBranch(*CurMBB, SuccBB, nullptr, Cond, dl);
482 SmallVector<MachineOperand, 0>(), dl);
1159 DebugLoc dl = PBB->findBranchDebugLoc(); local
1164 NewCond, dl);
1426 DebugLoc dl = getBranchDebugLoc(PrevBB); local
1430 TII->insertBranch(PrevBB, PriorTBB, nullptr, PriorCond, dl);
1484 DebugLoc dl = getBranchDebugLoc(PrevBB); local
1486 TII->insertBranch(PrevBB, PriorTBB, nullptr, PriorCond, dl);
1498 DebugLoc dl local
1536 DebugLoc dl = getBranchDebugLoc(PrevBB); local
1606 DebugLoc dl = getBranchDebugLoc(*MBB); local
1620 DebugLoc dl = getBranchDebugLoc(*MBB); local
[all...]
/freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/
H A DTargetInfo.cpp8349 CoerceBuilder(llvm::LLVMContext &c, const llvm::DataLayout &dl)
8350 : Context(c), DL(dl), Size(0), InReg(false) {}
/freebsd-11-stable/share/mk/
H A Dsrc.libnames.mk91 dl \
/freebsd-11-stable/contrib/file/src/
H A Dsoftmagic.c1998 double dl, dv; local
2080 dl = m->value.d;
2088 matched = dv != dl;
2092 matched = dv == dl;
2096 matched = dv > dl;
2100 matched = dv < dl;
/freebsd-11-stable/contrib/apr/include/
H A Dapr_portable.h170 #include <dl.h>
/freebsd-11-stable/contrib/apr/
H A Dconfigure23192 dl.h \
23270 dl.h \
26073 # Some -aix5 will use dl, no hassles. Keep that pattern here.
/freebsd-11-stable/sys/i386/i386/
H A Dsupport.s717 movb %dl,%bh

Completed in 601 milliseconds

1234567891011>>