/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 640 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 654 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 693 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 710 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 712 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 717 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 719 MI.addOperand(MCOperand::createReg(getRe [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMInstrInfo.cpp | 40 NopInst.addOperand(MCOperand::createReg(0)); 43 NopInst.addOperand(MCOperand::createReg(ARM::R0)); 44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); 46 NopInst.addOperand(MCOperand::createReg(0)); 47 NopInst.addOperand(MCOperand::createReg(0));
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H A D | Thumb1InstrInfo.cpp | 28 NopInst.addOperand(MCOperand::createReg(ARM::R8)); 29 NopInst.addOperand(MCOperand::createReg(ARM::R8)); 31 NopInst.addOperand(MCOperand::createReg(0));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/ |
H A D | PPCDisassembler.cpp | 78 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); 213 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 220 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 225 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 241 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 243 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 246 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 261 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 276 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 291 Inst.addOperand(MCOperand::createReg(RRegsNoR [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
H A D | MCInstBuilder.h | 32 Inst.addOperand(MCOperand::createReg(Reg));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/Disassembler/ |
H A D | SystemZDisassembler.cpp | 88 Inst.addOperand(MCOperand::createReg(RegNo)); 296 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); 306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); 317 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); 319 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); 329 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); 331 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); 341 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); 353 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); 365 Inst.addOperand(MCOperand::createReg(Bas [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/ |
H A D | LanaiDisassembler.cpp | 170 Inst.addOperand(MCOperand::createReg(Reg)); 179 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); 191 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); 193 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); 203 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/ |
H A D | X86Disassembler.cpp | 1762 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); 1830 MCOperand baseReg = MCOperand::createReg(baseRegNo); 1834 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); 1855 MCOperand baseReg = MCOperand::createReg(baseRegNo); 1941 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); 1944 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4))); 1947 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4))); 1961 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); 1994 mcInst.addOperand(MCOperand::createReg(X86::x)); break; 2039 baseReg = MCOperand::createReg(X8 [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsTargetStreamer.cpp | 170 TmpInst.addOperand(MCOperand::createReg(Reg0)); 179 TmpInst.addOperand(MCOperand::createReg(Reg0)); 192 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); 210 TmpInst.addOperand(MCOperand::createReg(Reg0)); 211 TmpInst.addOperand(MCOperand::createReg(Reg1)); 220 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); 228 TmpInst.addOperand(MCOperand::createReg(Reg0)); 229 TmpInst.addOperand(MCOperand::createReg(Reg1)); 230 TmpInst.addOperand(MCOperand::createReg(Reg2)); 248 TmpInst.addOperand(MCOperand::createReg(Reg [all...] |
H A D | MipsNaClELFStreamer.cpp | 105 MaskInst.addOperand(MCOperand::createReg(AddrReg)); 106 MaskInst.addOperand(MCOperand::createReg(AddrReg)); 107 MaskInst.addOperand(MCOperand::createReg(MaskReg));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFMCInstLower.cpp | 62 MCOp = MCOperand::createReg(MO.getReg());
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/Disassembler/ |
H A D | BPFDisassembler.cpp | 107 Inst.addOperand(MCOperand::createReg(Reg)); 122 Inst.addOperand(MCOperand::createReg(Reg)); 129 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); 210 Instr.addOperand(MCOperand::createReg(BPF::R6));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
H A D | VEMCInstLower.cpp | 44 return MCOperand::createReg(MO.getReg());
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
H A D | X86Operand.h | 496 Inst.addOperand(MCOperand::createReg(getReg())); 504 Inst.addOperand(MCOperand::createReg(RegNo)); 538 Inst.addOperand(MCOperand::createReg(Reg)); 543 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); 545 Inst.addOperand(MCOperand::createReg(getMemIndexReg())); 547 Inst.addOperand(MCOperand::createReg(getMemSegReg())); 561 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); 562 Inst.addOperand(MCOperand::createReg(getMemSegReg())); 567 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); 577 Inst.addOperand(MCOperand::createReg(getMemSegRe [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64AsmPrinter.cpp | 953 MOVI.addOperand(MCOperand::createReg(DestReg)); 962 FMov.addOperand(MCOperand::createReg(DestReg)); 963 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); 967 FMov.addOperand(MCOperand::createReg(DestReg)); 968 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); 972 FMov.addOperand(MCOperand::createReg(DestReg)); 973 FMov.addOperand(MCOperand::createReg(AArch64::XZR)); 1037 MovZ.addOperand(MCOperand::createReg(DestReg)); 1044 MovK.addOperand(MCOperand::createReg(DestReg)); 1045 MovK.addOperand(MCOperand::createReg(DestRe [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/ |
H A D | RISCVDisassembler.cpp | 72 Inst.addOperand(MCOperand::createReg(Reg)); 83 Inst.addOperand(MCOperand::createReg(Reg)); 94 Inst.addOperand(MCOperand::createReg(Reg)); 105 Inst.addOperand(MCOperand::createReg(Reg)); 116 Inst.addOperand(MCOperand::createReg(Reg)); 147 Inst.addOperand(MCOperand::createReg(Reg));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcMCInstLower.cpp | 75 return MCOperand::createReg(MO.getReg());
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
H A D | RISCVAsmBackend.cpp | 90 Res.addOperand(MCOperand::createReg(RISCV::X0)); 97 Res.addOperand(MCOperand::createReg(RISCV::X0)); 103 Res.addOperand(MCOperand::createReg(RISCV::X0)); 109 Res.addOperand(MCOperand::createReg(RISCV::X1));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 2346 Inst.addOperand(MCOperand::createReg(RegNum)); 2353 Inst.addOperand(MCOperand::createReg(RegNum)); 2370 Inst.addOperand(MCOperand::createReg(RegNum)); 2405 Inst.addOperand(MCOperand::createReg(getReg())); 2410 Inst.addOperand(MCOperand::createReg(getReg())); 2417 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg)); 2418 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); 2427 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg)); 2445 Inst.addOperand(MCOperand::createReg(*I)); 2453 Inst.addOperand(MCOperand::createReg(* [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
H A D | SparcDisassembler.cpp | 152 Inst.addOperand(MCOperand::createReg(Reg)); 163 Inst.addOperand(MCOperand::createReg(Reg)); 175 Inst.addOperand(MCOperand::createReg(Reg)); 187 Inst.addOperand(MCOperand::createReg(Reg)); 202 Inst.addOperand(MCOperand::createReg(Reg)); 213 Inst.addOperand(MCOperand::createReg(Reg)); 222 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo])); 231 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo])); 240 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); 255 Inst.addOperand(MCOperand::createReg(RegisterPai [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiMCInstLower.cpp | 105 MCOp = MCOperand::createReg(MO.getReg());
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430MCInstLower.cpp | 129 MCOp = MCOperand::createReg(MO.getReg());
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVMCInstLower.cpp | 99 MCOp = MCOperand::createReg(MO.getReg());
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZMCInstLower.cpp | 82 return MCOperand::createReg(MO.getReg());
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreMCInstLower.cpp | 86 return MCOperand::createReg(MO.getReg());
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