| /freebsd-11-stable/sys/contrib/octeon-sdk/ |
| H A D | cvmx-mpi-defs.h | 124 uint64_t clkdiv : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV) | NS member in struct:cvmx_mpi_cfg::cvmx_mpi_cfg_s
190 uint64_t clkdiv : 13;
197 uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV) member in struct:cvmx_mpi_cfg::cvmx_mpi_cfg_cn30xx
244 uint64_t clkdiv : 13;
251 uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV) member in struct:cvmx_mpi_cfg::cvmx_mpi_cfg_cn31xx
294 uint64_t clkdiv : 13;
302 uint64_t clkdiv : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV) | NS member in struct:cvmx_mpi_cfg::cvmx_mpi_cfg_cn61xx
361 uint64_t clkdiv : 13;
368 uint64_t clkdiv : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV) | NS member in struct:cvmx_mpi_cfg::cvmx_mpi_cfg_cn66xx
427 uint64_t clkdiv
[all...] |
| H A D | cvmx-llm.c | 351 int clkdiv = 2; /* CN38XX is fixed at 2, CN58XX supports 2,3,4 */ local
412 clkdiv = eclk_mhz/max_llm_clock_mhz;
413 if (clkdiv * max_llm_clock_mhz < eclk_mhz)
414 clkdiv++;
416 if (clkdiv > 4)
421 if (clkdiv < 2)
422 clkdiv = 2;
424 cvmx_dprintf("Using llm clock divisor: %d, llm clock is: %lu MHz\n", clkdiv, (unsigned long)eclk_mhz/clkdiv);
431 if (clkdiv
[all...] |
| H A D | cvmx-dfa-defs.h | 3499 uint64_t clkdiv : 2; /**< RLDCLK Divisor Select member in struct:cvmx_dfa_memcfg0::cvmx_dfa_memcfg0_s
3774 uint64_t clkdiv : 2;
|
| /freebsd-11-stable/sys/arm/ti/am335x/ |
| H A D | am335x_ehrpwm.c | 176 int clkdiv; local
178 clkdiv = am335x_ehrpwm_clkdiv[sc->sc_pwm_clkdiv];
179 sc->sc_pwm_freq = PWM_CLOCK / (1 * clkdiv) / sc->sc_pwm_period;
185 int clkdiv, error, freq, i, period; local
205 clkdiv = am335x_ehrpwm_clkdiv[i];
206 period = PWM_CLOCK / clkdiv / freq;
217 /* Update the clkdiv settings. */
234 int error, i, clkdiv; local
241 clkdiv = am335x_ehrpwm_clkdiv[sc->sc_pwm_clkdiv];
244 error = sysctl_handle_int(oidp, &clkdiv, sizeo
[all...] |
| /freebsd-11-stable/sys/arm/ti/ |
| H A D | ti_sdhci.c | 165 uint32_t clkdiv, val32; local
182 clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) &
185 val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
187 val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) &
256 uint32_t clkdiv, val32; local
264 clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK;
266 clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) &
268 clkdiv *= 2;
269 if (clkdiv > MMCHS_SYSCTL_CLKD_MASK)
270 clkdiv
[all...] |
| H A D | ti_spi.c | 125 uint32_t clkdiv, conf, div, extclk, reg; local
127 clkdiv = TI_SPI_GCLK / freq;
128 if (clkdiv > MCSPI_EXTCLK_MSK) {
130 clkdiv = 0;
132 while (TI_SPI_GCLK / div > freq && clkdiv <= 0xf) {
133 clkdiv++;
136 conf = clkdiv << MCSPI_CONF_CLK_SHIFT;
138 extclk = clkdiv >> 4;
139 clkdiv &= MCSPI_CONF_CLK_MSK;
140 conf = MCSPI_CONF_CLKG | clkdiv << MCSPI_CONF_CLK_SHIF
[all...] |
| /freebsd-11-stable/sys/arm/at91/ |
| H A D | at91_mci.c | 554 uint32_t clkdiv; local
574 clkdiv = 0;
578 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
580 clkdiv = (at91_master_clock / ios->clock) / 2;
581 freq = at91_master_clock / ((clkdiv+1) * 2);
582 if (clkdiv == 1 && ios->clock == 25000000 && freq <= 15000000) {
584 clkdiv = 0;
585 freq = at91_master_clock / ((clkdiv+1) * 2);
594 WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv);
|
| /freebsd-11-stable/sys/arm/lpc/ |
| H A D | lpc_mmc.c | 628 uint32_t clkdiv = 0, pwr = 0; local
631 clkdiv |= LPC_SD_CLOCK_WIDEBUS;
634 clkdiv = (LPC_SD_CLK / (2 * ios->clock)) - 1;
637 if ((LPC_SD_CLK / (2 * (clkdiv + 1))) > ios->clock)
638 clkdiv++;
640 debugf("clock: %dHz, clkdiv: %d\n", ios->clock, clkdiv);
644 clkdiv |= LPC_SD_CLOCK_WIDEBUS;
647 lpc_mmc_write_4(sc, LPC_SD_CLOCK, clkdiv | LPC_SD_CLOCK_ENABLE);
|
| /freebsd-11-stable/sys/arm/freescale/imx/ |
| H A D | imx_i2c.c | 108 struct clkdiv { struct
112 static struct clkdiv clkdiv_table[] = {
|
| /freebsd-11-stable/sys/dev/cxgb/common/ |
| H A D | cxgb_t3_hw.c | 252 u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1; local
253 u32 val = F_PREEN | V_CLKDIV(clkdiv);
|