/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 581 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, 582 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, 583 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, 584 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, 585 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 1}, 586 {ISD::VECTOR_SHUFFLE, MVT::v8i8, 1}, 588 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 1}, 589 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1}, 590 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 1}, 591 {ISD::VECTOR_SHUFFLE, MV [all...] |
H A D | ARMISelLowering.cpp | 183 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 258 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 320 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 410 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 940 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 7619 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 7620 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 9337 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG, Subtarget); 13017 /// ISD::VECTOR_SHUFFLE. 13020 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE doe [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 414 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as 415 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int 421 VECTOR_SHUFFLE, enumerator in enum:llvm::ISD::NodeType
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H A D | SelectionDAGNodes.h | 1515 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {} 1560 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 69 setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal); 70 setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal); 112 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteV); 164 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteW);
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H A D | HexagonISelLowering.cpp | 1493 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE 1578 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom); 1579 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 1580 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); 2909 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
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H A D | HexagonISelDAGToDAG.cpp | 903 case ISD::VECTOR_SHUFFLE: return SelectHvxShuffle(N);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 141 setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom); 144 setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom); 1028 case ISD::VECTOR_SHUFFLE:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 286 case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
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H A D | SelectionDAG.cpp | 631 case ISD::VECTOR_SHUFFLE: { 1612 "Invalid VECTOR_SHUFFLE"); 1755 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops); 2309 case ISD::VECTOR_SHUFFLE: { 2394 case ISD::VECTOR_SHUFFLE: { 2559 case ISD::VECTOR_SHUFFLE: { 3551 case ISD::VECTOR_SHUFFLE: { 5593 case ISD::VECTOR_SHUFFLE:
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H A D | LegalizeVectorTypes.cpp | 65 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; 852 case ISD::VECTOR_SHUFFLE: 2701 case ISD::VECTOR_SHUFFLE:
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H A D | DAGCombiner.cpp | 1610 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 4485 if (HandOpcode == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) { 11353 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() && 16738 if (Vec.getOpcode() == ISD::VECTOR_SHUFFLE && Vec.hasOneUse() && 17155 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 17161 if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) { 17195 TLI.isOperationExpand(ISD::VECTOR_SHUFFLE, VecVT)) { 17484 !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, InVT1)) 17642 if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VT)) 18232 // Fold CONCAT_VECTORS of EXTRACT_SUBVECTOR (or undef) to VECTOR_SHUFFLE [all...] |
H A D | TargetLowering.cpp | 760 case ISD::VECTOR_SHUFFLE: { 995 case ISD::VECTOR_SHUFFLE: { 2439 case ISD::VECTOR_SHUFFLE: {
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H A D | LegalizeDAG.cpp | 3033 case ISD::VECTOR_SHUFFLE: { 4406 case ISD::VECTOR_SHUFFLE: {
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H A D | LegalizeIntegerTypes.cpp | 97 case ISD::VECTOR_SHUFFLE:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 345 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 637 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 4505 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) { 4690 // Represent the BUILD_VECTOR as an N-operand VECTOR_SHUFFLE-like operation 5189 case ISD::VECTOR_SHUFFLE: 5460 else if ((Opcode == ISD::VECTOR_SHUFFLE || Opcode == SystemZISD::SPLAT) && 5805 Op1.getOpcode() == ISD::VECTOR_SHUFFLE && 5847 // First, combine the VECTOR_SHUFFLE away. This makes the value produced 6387 case ISD::VECTOR_SHUFFLE: return combineVECTOR_SHUFFLE(N, DCI);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 631 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 632 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 710 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 836 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal); 879 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal); 1010 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom); 1058 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom); 1099 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom); 1191 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1849 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operan [all...] |
H A D | PPCISelDAGToDAG.cpp | 4990 case ISD::VECTOR_SHUFFLE:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 307 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand); 308 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand); 309 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand); 310 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand); 637 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f16, Custom); 638 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 4070 case ISD::VECTOR_SHUFFLE:
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H A D | AMDGPUISelLowering.cpp | 394 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand); 430 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 1643 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 351 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom); 467 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); 2189 // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle 2536 // Lower VECTOR_SHUFFLE into SHF (if possible). 2627 // Determine whether VECTOR_SHUFFLE is a SPLATI. 2652 // Lower VECTOR_SHUFFLE into ILVEV (if possible). 2698 // Lower VECTOR_SHUFFLE into ILVOD (if possible). 2744 // Lower VECTOR_SHUFFLE into ILVR (if possible). 2791 // Lower VECTOR_SHUFFLE into ILVL (if possible). 2840 // Lower VECTOR_SHUFFLE int [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 846 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 942 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 949 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 1345 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 1434 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 1614 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 1748 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 1793 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom); 1794 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom); 1984 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 391 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f16, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 895 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 3223 case ISD::VECTOR_SHUFFLE:
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