Searched refs:VECREDUCE_UMIN (Results 1 - 12 of 12) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h939 VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp448 case ISD::VECREDUCE_UMIN: return "vecreduce_umin";
H A DLegalizeVectorOps.cpp482 case ISD::VECREDUCE_UMIN:
986 case ISD::VECREDUCE_UMIN:
H A DLegalizeVectorTypes.cpp614 case ISD::VECREDUCE_UMIN:
1994 case ISD::VECREDUCE_UMIN:
2080 case ISD::VECREDUCE_UMIN: CombineOpc = ISD::UMIN; break;
4235 case ISD::VECREDUCE_UMIN:
4700 case ISD::VECREDUCE_UMIN:
H A DLegalizeIntegerTypes.cpp198 case ISD::VECREDUCE_UMIN:
1333 case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break;
1760 case ISD::VECREDUCE_UMIN:
1939 case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break;
H A DLegalizeDAG.cpp1158 case ISD::VECREDUCE_UMIN:
3807 case ISD::VECREDUCE_UMIN:
H A DTargetLowering.cpp7625 case ISD::VECREDUCE_UMIN: BaseOpcode = ISD::UMIN; break;
H A DDAGCombiner.cpp1630 case ISD::VECREDUCE_UMIN:
19762 ? ISD::VECREDUCE_UMIN : ISD::VECREDUCE_UMAX;
H A DSelectionDAGBuilder.cpp9005 Res = DAG.getNode(ISD::VECREDUCE_UMIN, dl, VT, Op1);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp722 setOperationAction(ISD::VECREDUCE_UMIN, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp787 setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
3272 case ISD::VECREDUCE_UMIN:
8555 case ISD::VECREDUCE_UMIN:
12936 case ISD::VECREDUCE_UMIN:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp294 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);

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