Searched refs:VECREDUCE_UMIN (Results 1 - 12 of 12) sorted by relevance
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 939 VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN, enumerator in enum:llvm::ISD::NodeType
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 448 case ISD::VECREDUCE_UMIN: return "vecreduce_umin";
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H A D | LegalizeVectorOps.cpp | 482 case ISD::VECREDUCE_UMIN: 986 case ISD::VECREDUCE_UMIN:
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H A D | LegalizeVectorTypes.cpp | 614 case ISD::VECREDUCE_UMIN: 1994 case ISD::VECREDUCE_UMIN: 2080 case ISD::VECREDUCE_UMIN: CombineOpc = ISD::UMIN; break; 4235 case ISD::VECREDUCE_UMIN: 4700 case ISD::VECREDUCE_UMIN:
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H A D | LegalizeIntegerTypes.cpp | 198 case ISD::VECREDUCE_UMIN: 1333 case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break; 1760 case ISD::VECREDUCE_UMIN: 1939 case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break;
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H A D | LegalizeDAG.cpp | 1158 case ISD::VECREDUCE_UMIN: 3807 case ISD::VECREDUCE_UMIN:
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H A D | TargetLowering.cpp | 7625 case ISD::VECREDUCE_UMIN: BaseOpcode = ISD::UMIN; break;
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H A D | DAGCombiner.cpp | 1630 case ISD::VECREDUCE_UMIN: 19762 ? ISD::VECREDUCE_UMIN : ISD::VECREDUCE_UMAX;
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H A D | SelectionDAGBuilder.cpp | 9005 Res = DAG.getNode(ISD::VECREDUCE_UMIN, dl, VT, Op1);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 722 setOperationAction(ISD::VECREDUCE_UMIN, VT, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 787 setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom); 3272 case ISD::VECREDUCE_UMIN: 8555 case ISD::VECREDUCE_UMIN: 12936 case ISD::VECREDUCE_UMIN:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 294 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);
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