Searched refs:VECREDUCE_UMAX (Results 1 - 12 of 12) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h939 VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp447 case ISD::VECREDUCE_UMAX: return "vecreduce_umax";
H A DLegalizeVectorOps.cpp481 case ISD::VECREDUCE_UMAX:
985 case ISD::VECREDUCE_UMAX:
H A DLegalizeVectorTypes.cpp613 case ISD::VECREDUCE_UMAX:
1993 case ISD::VECREDUCE_UMAX:
2079 case ISD::VECREDUCE_UMAX: CombineOpc = ISD::UMAX; break;
4234 case ISD::VECREDUCE_UMAX:
4693 case ISD::VECREDUCE_UMAX:
H A DLegalizeIntegerTypes.cpp197 case ISD::VECREDUCE_UMAX:
1332 case ISD::VECREDUCE_UMAX:
1759 case ISD::VECREDUCE_UMAX:
1938 case ISD::VECREDUCE_UMAX:
H A DLegalizeDAG.cpp1157 case ISD::VECREDUCE_UMAX:
3806 case ISD::VECREDUCE_UMAX:
H A DTargetLowering.cpp7624 case ISD::VECREDUCE_UMAX: BaseOpcode = ISD::UMAX; break;
H A DDAGCombiner.cpp1629 case ISD::VECREDUCE_UMAX:
19762 ? ISD::VECREDUCE_UMIN : ISD::VECREDUCE_UMAX;
H A DSelectionDAGBuilder.cpp9002 Res = DAG.getNode(ISD::VECREDUCE_UMAX, dl, VT, Op1);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp721 setOperationAction(ISD::VECREDUCE_UMAX, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp786 setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
3271 case ISD::VECREDUCE_UMAX:
8553 case ISD::VECREDUCE_UMAX:
12935 case ISD::VECREDUCE_UMAX:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp292 setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal);

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