Searched refs:VECREDUCE_SMIN (Results 1 - 12 of 12) sorted by relevance
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 939 VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN, enumerator in enum:llvm::ISD::NodeType
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 446 case ISD::VECREDUCE_SMIN: return "vecreduce_smin";
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H A D | LegalizeVectorOps.cpp | 480 case ISD::VECREDUCE_SMIN: 984 case ISD::VECREDUCE_SMIN:
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H A D | LegalizeVectorTypes.cpp | 612 case ISD::VECREDUCE_SMIN: 1992 case ISD::VECREDUCE_SMIN: 2078 case ISD::VECREDUCE_SMIN: CombineOpc = ISD::SMIN; break; 4233 case ISD::VECREDUCE_SMIN: 4707 case ISD::VECREDUCE_SMIN:
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H A D | LegalizeIntegerTypes.cpp | 196 case ISD::VECREDUCE_SMIN: 1331 case ISD::VECREDUCE_SMIN: 1756 case ISD::VECREDUCE_SMIN: 1937 case ISD::VECREDUCE_SMIN:
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H A D | LegalizeDAG.cpp | 1156 case ISD::VECREDUCE_SMIN: 3805 case ISD::VECREDUCE_SMIN:
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H A D | TargetLowering.cpp | 7623 case ISD::VECREDUCE_SMIN: BaseOpcode = ISD::SMIN; break;
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H A D | SelectionDAGBuilder.cpp | 8999 Res = DAG.getNode(ISD::VECREDUCE_SMIN, dl, VT, Op1);
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H A D | DAGCombiner.cpp | 1628 case ISD::VECREDUCE_SMIN:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 720 setOperationAction(ISD::VECREDUCE_SMIN, VT, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 785 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom); 3270 case ISD::VECREDUCE_SMIN: 8551 case ISD::VECREDUCE_SMIN: 12934 case ISD::VECREDUCE_SMIN:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 293 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);
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