Searched refs:VECREDUCE_SMIN (Results 1 - 12 of 12) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h939 VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp446 case ISD::VECREDUCE_SMIN: return "vecreduce_smin";
H A DLegalizeVectorOps.cpp480 case ISD::VECREDUCE_SMIN:
984 case ISD::VECREDUCE_SMIN:
H A DLegalizeVectorTypes.cpp612 case ISD::VECREDUCE_SMIN:
1992 case ISD::VECREDUCE_SMIN:
2078 case ISD::VECREDUCE_SMIN: CombineOpc = ISD::SMIN; break;
4233 case ISD::VECREDUCE_SMIN:
4707 case ISD::VECREDUCE_SMIN:
H A DLegalizeIntegerTypes.cpp196 case ISD::VECREDUCE_SMIN:
1331 case ISD::VECREDUCE_SMIN:
1756 case ISD::VECREDUCE_SMIN:
1937 case ISD::VECREDUCE_SMIN:
H A DLegalizeDAG.cpp1156 case ISD::VECREDUCE_SMIN:
3805 case ISD::VECREDUCE_SMIN:
H A DTargetLowering.cpp7623 case ISD::VECREDUCE_SMIN: BaseOpcode = ISD::SMIN; break;
H A DSelectionDAGBuilder.cpp8999 Res = DAG.getNode(ISD::VECREDUCE_SMIN, dl, VT, Op1);
H A DDAGCombiner.cpp1628 case ISD::VECREDUCE_SMIN:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp720 setOperationAction(ISD::VECREDUCE_SMIN, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp785 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
3270 case ISD::VECREDUCE_SMIN:
8551 case ISD::VECREDUCE_SMIN:
12934 case ISD::VECREDUCE_SMIN:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp293 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);

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