Searched refs:VECREDUCE_SMAX (Results 1 - 12 of 12) sorted by relevance
| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 939 VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN, enumerator in enum:llvm::ISD::NodeType
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 445 case ISD::VECREDUCE_SMAX: return "vecreduce_smax";
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| H A D | LegalizeVectorOps.cpp | 479 case ISD::VECREDUCE_SMAX:
983 case ISD::VECREDUCE_SMAX:
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| H A D | LegalizeVectorTypes.cpp | 611 case ISD::VECREDUCE_SMAX:
1991 case ISD::VECREDUCE_SMAX:
2077 case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break;
4232 case ISD::VECREDUCE_SMAX:
4703 case ISD::VECREDUCE_SMAX:
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| H A D | LegalizeIntegerTypes.cpp | 195 case ISD::VECREDUCE_SMAX:
1330 case ISD::VECREDUCE_SMAX:
1755 case ISD::VECREDUCE_SMAX:
1936 case ISD::VECREDUCE_SMAX:
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| H A D | LegalizeDAG.cpp | 1155 case ISD::VECREDUCE_SMAX:
3804 case ISD::VECREDUCE_SMAX:
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| H A D | TargetLowering.cpp | 7622 case ISD::VECREDUCE_SMAX: BaseOpcode = ISD::SMAX; break;
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| H A D | SelectionDAGBuilder.cpp | 8996 Res = DAG.getNode(ISD::VECREDUCE_SMAX, dl, VT, Op1);
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| H A D | DAGCombiner.cpp | 1627 case ISD::VECREDUCE_SMAX:
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 719 setOperationAction(ISD::VECREDUCE_SMAX, VT, Expand);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 784 setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
3269 case ISD::VECREDUCE_SMAX:
8549 case ISD::VECREDUCE_SMAX:
12933 case ISD::VECREDUCE_SMAX:
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 291 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal);
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