Searched refs:VECREDUCE_FMIN (Results 1 - 10 of 10) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h933 VECREDUCE_FMAX, VECREDUCE_FMIN, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp450 case ISD::VECREDUCE_FMIN: return "vecreduce_fmin";
H A DLegalizeVectorOps.cpp486 case ISD::VECREDUCE_FMIN:
990 case ISD::VECREDUCE_FMIN:
H A DLegalizeVectorTypes.cpp616 case ISD::VECREDUCE_FMIN:
1996 case ISD::VECREDUCE_FMIN:
2084 case ISD::VECREDUCE_FMIN:
4237 case ISD::VECREDUCE_FMIN:
4721 case ISD::VECREDUCE_FMIN:
H A DLegalizeDAG.cpp1160 case ISD::VECREDUCE_FMIN:
3809 case ISD::VECREDUCE_FMIN:
H A DTargetLowering.cpp7629 case ISD::VECREDUCE_FMIN:
H A DSelectionDAGBuilder.cpp9011 Res = DAG.getNode(ISD::VECREDUCE_FMIN, dl, VT, Op1);
H A DDAGCombiner.cpp1632 case ISD::VECREDUCE_FMIN: return visitVECREDUCE(N);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp724 setOperationAction(ISD::VECREDUCE_FMIN, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp798 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
3274 case ISD::VECREDUCE_FMIN:
8564 case ISD::VECREDUCE_FMIN: {

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