Searched refs:VECREDUCE_AND (Results 1 - 10 of 10) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h938 VECREDUCE_AND, VECREDUCE_OR, VECREDUCE_XOR, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp442 case ISD::VECREDUCE_AND: return "vecreduce_and";
H A DLegalizeVectorOps.cpp476 case ISD::VECREDUCE_AND:
980 case ISD::VECREDUCE_AND:
H A DLegalizeVectorTypes.cpp608 case ISD::VECREDUCE_AND:
1988 case ISD::VECREDUCE_AND:
2074 case ISD::VECREDUCE_AND: CombineOpc = ISD::AND; break;
4229 case ISD::VECREDUCE_AND:
4699 case ISD::VECREDUCE_AND:
H A DLegalizeIntegerTypes.cpp192 case ISD::VECREDUCE_AND:
1327 case ISD::VECREDUCE_AND:
1750 case ISD::VECREDUCE_AND:
1933 case ISD::VECREDUCE_AND:
H A DLegalizeDAG.cpp1152 case ISD::VECREDUCE_AND:
3801 case ISD::VECREDUCE_AND:
H A DDAGCombiner.cpp1624 case ISD::VECREDUCE_AND:
19760 if (Opcode == ISD::VECREDUCE_AND || Opcode == ISD::VECREDUCE_OR) {
19761 unsigned NewOpcode = Opcode == ISD::VECREDUCE_AND
H A DTargetLowering.cpp7619 case ISD::VECREDUCE_AND: BaseOpcode = ISD::AND; break;
H A DSelectionDAGBuilder.cpp8987 Res = DAG.getNode(ISD::VECREDUCE_AND, dl, VT, Op1);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp716 setOperationAction(ISD::VECREDUCE_AND, VT, Expand);

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