Searched refs:UMAX (Results 1 - 25 of 32) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h445 SMIN, SMAX, UMIN, UMAX, enumerator in enum:llvm::ISD::NodeType
H A DTargetLowering.h2242 case ISD::UMAX:
/freebsd-11-stable/contrib/gcc/
H A Dsched-vis.c160 case UMAX:
H A Dcollect2.c79 #ifdef UMAX
H A Dcombine.c4351 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5026 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
7464 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7470 || code == UMAX)
7670 || code == UMIN || code == UMAX)
7672 int unsignedp = (code == UMIN || code == UMAX);
7678 if ((code == SMAX || code == UMAX)
H A Dsimplify-rtx.c1396 SMIN, SMAX, UMIN or UMAX. Return zero if no simplification or
2529 case UMAX:
2980 case UMAX:
3164 case UMAX:
H A Drtlanal.c3617 case UMIN: case UMAX: case SMIN: case SMAX:
4127 case SMIN: case SMAX: case UMIN: case UMAX:
H A Difcvt.c1686 op = UMAX;
H A Dcse.c4333 case SMIN: case SMAX: case UMIN: case UMAX:
H A Doptabs.c5257 umax_optab = init_optab (UMAX);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp269 case ISD::UMAX: return "umax";
H A DLegalizeIntegerTypes.cpp84 case ISD::UMAX: Res = PromoteIntRes_ZExtIntBinOp(N); break;
733 DAG.getNode(ISD::UMAX, dl, PromotedType, Op1Promoted, Op2Promoted);
1890 case ISD::UMAX:
2221 return std::make_pair(ISD::SETGT, ISD::UMAX);
2222 case ISD::UMAX:
2223 return std::make_pair(ISD::SETUGT, ISD::UMAX);
H A DLegalizeVectorTypes.cpp123 case ISD::UMAX:
934 case ISD::UMAX:
2079 case ISD::VECREDUCE_UMAX: CombineOpc = ISD::UMAX; break;
2726 case ISD::UMAX:
H A DLegalizeVectorOps.cpp445 case ISD::UMAX:
H A DTargetLowering.cpp7107 if (Opcode == ISD::USUBSAT && isOperationLegalOrCustom(ISD::UMAX, VT)) {
7108 SDValue Max = DAG.getNode(ISD::UMAX, dl, VT, LHS, RHS);
7624 case ISD::VECREDUCE_UMAX: BaseOpcode = ISD::UMAX; break;
H A DLegalizeDAG.cpp3170 case ISD::UMAX: {
3177 case ISD::UMAX: Pred = ISD::SETUGT; break;
H A DSelectionDAG.cpp3347 case ISD::UMAX: {
3351 // UMAX - we know that the result will have the maximum of the
3722 case ISD::UMAX:
4802 case ISD::UMAX: return C1.uge(C2) ? C1 : C2;
5199 case ISD::UMAX:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp349 setOperationAction(ISD::UMAX, Ty, Legal);
2016 return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
2028 return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
/freebsd-11-stable/contrib/gcc/config/ia64/
H A Dia64.c1776 if (mode == V8QImode && (code == UMIN || code == UMAX))
1782 if (mode == V4HImode && code == UMAX)
1803 case UMAX:
5704 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp453 setOperationAction(ISD::UMAX, MVT::i16, Legal);
623 setOperationAction(ISD::UMAX, MVT::v2i16, Legal);
650 setOperationAction(ISD::UMAX, MVT::v4i16, Custom);
730 setTargetDAGCombine(ISD::UMAX);
4098 case ISD::UMAX:
9025 case ISD::UMAX:
9191 if (Opc == ISD::UMIN && Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) {
9316 case ISD::UMAX:
10009 case ISD::UMAX:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp649 setOperationAction(ISD::UMAX, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp186 for (auto Op : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp192 setOperationAction(ISD::UMAX, VT, Legal);
928 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
2969 return DAG.getNode(ISD::UMAX, dl, Op.getValueType(),
12956 ReplaceReductionResults(N, Results, DAG, ISD::UMAX, AArch64ISD::UMAXV);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp905 setOperationAction(ISD::UMAX, VT, VT == MVT::v16i8 ? Legal : Custom);
1085 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
1086 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
1285 setOperationAction(ISD::UMAX, MVT::v4i64, Custom);
1301 setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom);
1560 setOperationAction(ISD::UMAX, VT, Legal);
1672 setOperationAction(ISD::UMAX, VT, Legal);
1817 setOperationAction(ISD::UMAX, VT, Legal);
21616 case ISD::SETUGE: Opc = ISD::UMAX; break;
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp500 setOperationAction(ISD::UMAX, Ty, Legal);

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