Searched refs:Sub (Results 1 - 25 of 196) sorted by relevance

12345678

/freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/MCDisassembler/
H A DMCExternalSymbolizer.cpp100 const MCExpr *Sub = nullptr; local
105 Sub = MCSymbolRefExpr::create(Sym, Ctx);
107 Sub = MCConstantExpr::create((int)SymbolicOp.SubtractSymbol.Value, Ctx);
116 if (Sub) {
119 LHS = MCBinaryExpr::createSub(Add, Sub, Ctx);
121 LHS = MCUnaryExpr::createMinus(Sub, Ctx);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp179 Sub(Op.getSubReg()) {}
180 RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
183 return Reg == RR.Reg && Sub == RR.Sub;
187 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);
190 unsigned Reg, Sub; member in struct:__anon2239::HexagonExpandCondsets::RegisterRef
197 unsigned getMaskForSub(unsigned Sub);
199 LaneBitmask getLaneMask(unsigned Reg, unsigned Sub);
260 unsigned HexagonExpandCondsets::getMaskForSub(unsigned Sub) { argument
288 getLaneMask(unsigned Reg, unsigned Sub) argument
[all...]
H A DHexagonBitSimplify.cpp402 // For a register ref (pair Reg:Sub), set Begin to the position of the LSB
403 // of Sub in Reg, and set Width to the size of Sub in bits. Return true,
408 if (RR.Sub == 0) {
420 if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi)
892 // Calculate the register class that matches Reg:Sub. For example, if
900 if (RR.Sub == 0)
905 auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void {
907 assert(Sub
[all...]
H A DHexagonBitTracker.h39 BitTracker::BitMask mask(unsigned Reg, unsigned Sub) const override;
H A DBitTracker.cpp336 // 2. find a physical register PhysS that corresponds to PhysR:RR.Sub,
339 const auto &VC = composeWithSubRegIndex(*MRI.getRegClass(RR.Reg), RR.Sub);
344 (RR.Sub == 0) ? Register(RR.Reg) : TRI.getSubReg(RR.Reg, RR.Sub);
366 if (!RR.Sub)
368 BitMask M = mask(RR.Reg, RR.Sub);
382 assert(RR.Sub == 0 && "Unexpected sub-register in definition");
707 BT::BitMask BT::MachineEvaluator::mask(unsigned Reg, unsigned Sub) const {
708 assert(Sub == 0 && "Generic BitTracker::mask called for Sub !
[all...]
H A DHexagonBlockRanges.h34 unsigned Reg, Sub; member in struct:llvm::HexagonBlockRanges::RegisterRef
37 return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub);
H A DBitTracker.h142 : Reg(R), Sub(S) {}
144 : Reg(MO.getReg()), Sub(MO.getSubReg()) {}
146 unsigned Reg, Sub; member in struct:llvm::BitTracker::RegisterRef
458 // to the subregister Sub. These bits are assumed to be contiguous in
461 // Sub == 0, in this case, the function should return a mask that spans
464 virtual BitMask mask(unsigned Reg, unsigned Sub) const;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64ExternalSymbolizer.cpp182 const MCExpr *Sub = nullptr; local
187 Sub = MCSymbolRefExpr::create(Sym, Ctx);
189 Sub = MCConstantExpr::create(SymbolicOp.SubtractSymbol.Value, Ctx);
198 if (Sub) {
201 LHS = MCBinaryExpr::createSub(Add, Sub, Ctx);
203 LHS = MCUnaryExpr::createMinus(Sub, Ctx);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Support/
H A DCommandLine.cpp190 for (auto *Sub : RegisteredSubCommands) {
191 if (SC == Sub)
193 addLiteralOption(Opt, Sub, Name);
246 for (auto *Sub : RegisteredSubCommands) {
247 if (SC == Sub)
249 addOption(O, Sub);
274 SubCommand &Sub = *SC; local
275 auto End = Sub.OptionsMap.end();
277 auto I = Sub.OptionsMap.find(Name);
279 Sub
331 SubCommand &Sub = *SC; local
422 LookupLongOption(SubCommand &Sub, StringRef &Arg, StringRef &Value, bool LongOptionsUseDoubleDash, bool HaveDoubleDash) argument
522 LookupOption(SubCommand &Sub, StringRef &Arg, StringRef &Value) argument
2164 SubCommand *Sub = GlobalParser->getActiveSubCommand(); local
2549 getRegisteredOptions(SubCommand &Sub) argument
2561 HideUnrelatedOptions(cl::OptionCategory &Category, SubCommand &Sub) argument
2571 HideUnrelatedOptions(ArrayRef<const cl::OptionCategory *> Categories, SubCommand &Sub) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DDivRemPairs.cpp267 Instruction *Sub = BinaryOperator::CreateSub(X, Mul); local
302 Sub->insertAfter(Mul);
306 Sub->setName(RemInst->getName() + ".decomposed");
309 RemInst = Sub;
311 OrigRemInst->replaceAllUsesWith(Sub);
H A DReassociate.cpp905 if (TheNeg->getOpcode() == Instruction::Sub) {
923 static bool ShouldBreakUpSubtract(Instruction *Sub) { argument
925 if (match(Sub, m_Neg(m_Value())) || match(Sub, m_FNeg(m_Value())))
929 if (isa<UndefValue>(Sub->getOperand(1)))
934 Value *V0 = Sub->getOperand(0);
936 isReassociableOp(V0, Instruction::Sub, Instruction::FSub))
938 Value *V1 = Sub->getOperand(1);
940 isReassociableOp(V1, Instruction::Sub, Instruction::FSub))
942 Value *VB = Sub
953 BreakUpSubtract(Instruction *Sub, ReassociatePass::OrderedSet &ToRedo) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp59 case Instruction::Sub:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86WinAllocaExpander.cpp43 enum Lowering { TouchAndSub, Sub, Probe }; enumerator in enum:__anon2521::X86WinAllocaExpander::Lowering
104 return Sub;
162 case Sub:
229 case Sub:
237 // Sub.
255 // Sub
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUAtomicOptimizer.cpp123 case AtomicRMWInst::Sub:
176 Op = AtomicRMWInst::Sub;
255 case AtomicRMWInst::Sub:
256 return B.CreateBinOp(Instruction::Sub, LHS, RHS);
392 case AtomicRMWInst::Sub:
486 Op == AtomicRMWInst::Sub ? AtomicRMWInst::Add : Op;
522 case AtomicRMWInst::Sub: {
625 case AtomicRMWInst::Sub:
/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/scudo/
H A Dscudo_allocator_secondary.h159 Stats->Sub(AllocatorStatAllocated, Size);
160 Stats->Sub(AllocatorStatMapped, Size);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/
H A DTruncInstCombine.cpp51 case Instruction::Sub:
113 case Instruction::Sub:
344 case Instruction::Sub:
H A DAggressiveInstCombine.cpp81 auto Sub = m_Sub(m_SpecificInt(Width), m_Value(R1));
85 m_c_Or(m_Shl(m_Value(L0), m_Value(L1)), m_LShr(m_Value(R0), Sub)));
94 m_c_Or(m_LShr(m_Value(L0), m_Value(L1)), m_Shl(m_Value(R0), Sub)));
/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_allocator_stats.h38 void Sub(AllocatorStat i, uptr v) { function in class:AllocatorStats
/freebsd-11-stable/contrib/llvm-project/clang/lib/Basic/
H A DModule.cpp307 for (submodule_iterator Sub = Current->submodule_begin(),
309 Sub != SubEnd; ++Sub) {
310 if (needUpdate(*Sub))
311 Stack.push_back(*Sub);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DControlHeightReduction.cpp226 for (CHRScope *Sub : Next->Subs)
227 Subs.push_back(Sub);
263 CHRScope *Sub = *It; local
264 assert(Sub && "null Sub");
265 Region *Parent = Sub->getParentRegion();
267 TailSubs.push_back(Sub);
490 for (CHRScope *Sub : Subs) {
491 OS << *Sub << ", "; local
1034 for (CHRScope *Sub
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp303 MachineInstr *Sub = nullptr;
309 // BB as the comparison. Don't return if SFSUB_F_RI and CmpValue != 0 as Sub
318 // instruction we want to change while searching for Sub.
331 Sub = &*I;
341 if (!MI && !Sub)
346 MI = Sub;
374 if (Sub) {
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
383 Sub->getOperand(2).getReg() == SrcReg) {
388 // No Sub, s
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/
H A DOperator.h63 /// Utility class for integer operators which may exhibit overflow - Add, Sub,
102 I->getOpcode() == Instruction::Sub ||
108 CE->getOpcode() == Instruction::Sub ||
430 : public ConcreteOperator<OverflowingBinaryOperator, Instruction::Sub> {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/TableGen/
H A DSetTheory.cpp46 // (sub Add, Sub, ...) Set difference.
53 RecSet Add, Sub; variable
55 ST.evaluate(Expr->arg_begin() + 1, Expr->arg_end(), Sub, Loc);
57 if (!Sub.count(*I))
/freebsd-11-stable/contrib/llvm-project/clang/lib/Serialization/
H A DASTReaderStmt.cpp2192 SmallVector<Expr *, 4> Sub; local
2194 Sub.reserve(CollapsedNum);
2196 Sub.push_back(Record.readSubExpr());
2197 D->setCounters(Sub);
2198 Sub.clear();
2200 Sub.push_back(Record.readSubExpr());
2201 D->setPrivateCounters(Sub);
2202 Sub.clear();
2204 Sub.push_back(Record.readSubExpr());
2205 D->setInits(Sub);
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineAtomicRMW.cpp40 case AtomicRMWInst::Sub:

Completed in 323 milliseconds

12345678