Searched refs:SrcR (Results 1 - 7 of 7) sorted by relevance
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | RDFCopy.cpp | 47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); local 49 assert(Register::isPhysicalRegister(SrcR.Reg)); 52 TRI.getMinimalPhysRegClass(SrcR.Reg)) 54 EM.insert(std::make_pair(DstR, SrcR));
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H A D | HexagonGenInsert.cpp | 466 // ... = insert(SrcR, InsR, #Wdh, #Off) 469 : SrcR(SR), InsR(IR), Wdh(W), Off(O) {} 471 unsigned SrcR, InsR; 487 unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR; 488 OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI) 534 bool isValidInsertForm(unsigned DstR, unsigned SrcR, unsigned InsR, 684 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, 687 const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcR); 881 unsigned SrcR [all...] |
H A D | HexagonRDFOpt.cpp | 113 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { 114 EM.insert(std::make_pair(DstR, SrcR));
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H A D | HexagonFrameLowering.cpp | 1608 Register SrcR = MI->getOperand(1).getReg(); local 1610 !Hexagon::ModRegsRegClass.contains(SrcR)) 1632 Register SrcR = MI->getOperand(2).getReg(); local 1636 // TmpR = C2_tfrpr SrcR if SrcR is a predicate register 1637 // TmpR = A2_tfrcrr SrcR if SrcR is a modifier register 1642 .addReg(SrcR, getKillRegState(IsKill)); 1695 Register SrcR = MI->getOperand(2).getReg(); local 1711 .addReg(SrcR, getKillRegStat 1782 Register SrcR = MI->getOperand(2).getReg(); local 1882 Register SrcR = MI->getOperand(2).getReg(); local [all...] |
H A D | HexagonBitSimplify.cpp | 2210 unsigned SrcR = B0.RefI.Reg; 2219 if (V.RefI.Reg != SrcR || V.RefI.Pos != Pos+i) 2236 // The Z lower bits should now match SrcR. 2238 if (S0.Type != BitTracker::BitValue::Ref || S0.RefI.Reg != SrcR) 2255 if (V.RefI.Reg != SrcR || V.RefI.Pos != P+I) 2270 if (MRI.getRegClass(SrcR)->getID() == Hexagon::DoubleRegsRegClassID) 2272 if (!validateReg({SrcR,SrcSR}, Hexagon::A4_bitspliti, 1)) 2282 if (Op1.getReg() != SrcR || Op1.getSubReg() != SrcSR) 2301 .addReg(SrcR, 0, SrcSR)
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H A D | HexagonConstPropagation.cpp | 1944 RegisterSubReg SrcR(MI.getOperand(1)); 1945 bool Eval = evaluateCOPY(SrcR, Inputs, RC);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FixupLEAs.cpp | 517 const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index; local 519 .add(SrcR)
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