Searched refs:SMIN (Results 1 - 25 of 36) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2767 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN;
2783 {ISD::SMIN, MVT::v2i64, 6},
2785 {ISD::SMIN, MVT::v4i32, 6},
2787 {ISD::SMIN, MVT::v8i16, 4},
2789 {ISD::SMIN, MVT::v16i8, 8},
2795 {ISD::SMIN, MVT::v2i64, 9},
2797 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5"
2799 {ISD::SMIN, MVT::v8i16, 2},
2801 {ISD::SMIN, MVT::v16i8, 3},
2806 {ISD::SMIN, MV
[all...]
H A DX86ISelLowering.cpp904 setOperationAction(ISD::SMIN, VT, VT == MVT::v8i16 ? Legal : Custom);
1087 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
1088 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
1286 setOperationAction(ISD::SMIN, MVT::v4i64, Custom);
1302 setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom);
1561 setOperationAction(ISD::SMIN, VT, Legal);
1673 setOperationAction(ISD::SMIN, VT, Legal);
1818 setOperationAction(ISD::SMIN, VT, Legal);
[all...]
/freebsd-11-stable/usr.bin/calendar/
H A Dsunpos.c190 #define SMIN(s) (((s) % 3600) / 60) macro
244 dial, SHOUR(dial), SMIN(dial)); */
246 SHOUR(dial), SMIN(dial), SSEC(dial),
283 dial, SHOUR(dial), SMIN(dial)); */
285 SHOUR(dial), SMIN(dial), SSEC(dial),
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h445 SMIN, SMAX, UMIN, UMAX, enumerator in enum:llvm::ISD::NodeType
H A DTargetLowering.h2239 case ISD::SMIN:
/freebsd-11-stable/contrib/gcc/
H A Dsched-vis.c145 case SMIN:
H A Dexplow.c1548 case SMIN:
H A Dsimplify-rtx.c1396 SMIN, SMAX, UMIN or UMAX. Return zero if no simplification or
2492 case SMIN:
2950 case SMIN:
3151 case SMIN:
H A Drtlanal.c3617 case UMIN: case UMAX: case SMIN: case SMAX:
4127 case SMIN: case SMAX: case UMIN: case UMAX:
H A Dcombine.c4351 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5023 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
7669 else if (code == SMAX || code == SMIN
H A Difcvt.c1639 they will be resolved with an SMIN/SMAX. It wouldn't be too hard
1681 op = SMIN;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp98 setOperationAction(ISD::SMIN, MVT::i32, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp266 case ISD::SMIN: return "smin";
H A DLegalizeVectorTypes.cpp120 case ISD::SMIN:
931 case ISD::SMIN:
2078 case ISD::VECREDUCE_SMIN: CombineOpc = ISD::SMIN; break;
2723 case ISD::SMIN:
H A DLegalizeIntegerTypes.cpp81 case ISD::SMIN:
752 Result = DAG.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
1893 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
2224 case ISD::SMIN:
H A DLegalizeVectorOps.cpp442 case ISD::SMIN:
H A DSelectionDAG.cpp3361 case ISD::SMIN:
3368 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX))
3694 case ISD::SMIN:
3701 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX))
4799 case ISD::SMIN: return C1.sle(C2) ? C1 : C2;
5196 case ISD::SMIN:
H A DLegalizeDAG.cpp3167 case ISD::SMIN:
3176 case ISD::SMIN: Pred = ISD::SETLT; break;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp346 setOperationAction(ISD::SMIN, Ty, Legal);
2034 return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
2046 return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp449 setOperationAction(ISD::SMIN, MVT::i16, Legal);
620 setOperationAction(ISD::SMIN, MVT::v2i16, Legal);
647 setOperationAction(ISD::SMIN, MVT::v4i16, Custom);
727 setTargetDAGCombine(ISD::SMIN);
4095 case ISD::SMIN:
9030 case ISD::SMIN:
9186 if (Opc == ISD::SMIN && Op0.getOpcode() == ISD::SMAX && Op0.hasOneUse()) {
9317 case ISD::SMIN:
10008 case ISD::SMIN:
H A DAMDGPUISelLowering.cpp346 setOperationAction(ISD::SMIN, MVT::i32, Legal);
2671 B = DAG.getNode(ISD::SMIN, DL, MVT::i32, B,
/freebsd-11-stable/contrib/gcc/config/ia64/
H A Dia64.c1778 if (mode == V4HImode && (code == SMIN || code == SMAX))
1806 case SMIN:
5704 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp646 setOperationAction(ISD::SMIN, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp186 for (auto Op : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp193 setOperationAction(ISD::SMIN, VT, Legal);
928 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
2972 return DAG.getNode(ISD::SMIN, dl, Op.getValueType(),
12947 ReplaceReductionResults(N, Results, DAG, ISD::SMIN, AArch64ISD::SMINV);

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