Searched refs:SMAX (Results 1 - 25 of 36) sorted by relevance

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/freebsd-11-stable/contrib/ntp/ntpd/
H A Drefclock_as2201.c65 #define SMAX 200 /* statistics buffer length */ macro
79 char stats[SMAX]; /* statistics buffer */
267 if ((int)(up->lastptr - up->stats + pp->lencode) > SMAX - 2)
331 if ((int)(up->lastptr - up->stats + pp->lencode) > SMAX - 2)
337 if ((int)(up->lastptr - up->stats + 1 + octets) > SMAX - 2)
H A Drefclock_hpgps.c100 #define SMAX 23*80+1 /* for :SYSTEM:PRINT? status screen response */ macro
122 char statscrn[SMAX]; /* receiver status screen buffer */
302 if ((int)(pp->lencode + 2) <= (SMAX - (up->lastptr - up->statscrn))) {
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h445 SMIN, SMAX, UMIN, UMAX, enumerator in enum:llvm::ISD::NodeType
H A DTargetLowering.h2240 case ISD::SMAX:
/freebsd-11-stable/contrib/gcc/
H A Dsched-vis.c150 case SMAX:
H A Dexplow.c1551 case SMAX:
H A Dsimplify-rtx.c1396 SMIN, SMAX, UMIN or UMAX. Return zero if no simplification or
2505 case SMAX:
2960 case SMAX:
3160 case SMAX:
H A Drtlanal.c3617 case UMIN: case UMAX: case SMIN: case SMAX:
4127 case SMIN: case SMAX: case UMIN: case UMAX:
H A Dcombine.c4351 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5020 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
7669 else if (code == SMAX || code == SMIN
7676 the value of 'SMAX (x, y)' when x is not equal to y,
7678 if ((code == SMAX || code == UMAX)
H A Difcvt.c1639 they will be resolved with an SMIN/SMAX. It wouldn't be too hard
1674 op = SMAX;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp97 setOperationAction(ISD::SMAX, MVT::i32, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp267 case ISD::SMAX: return "smax";
H A DLegalizeVectorTypes.cpp121 case ISD::SMAX:
932 case ISD::SMAX:
2077 case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break;
2724 case ISD::SMAX:
H A DLegalizeIntegerTypes.cpp82 case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break;
753 Result = DAG.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
1891 case ISD::SMAX:
2220 case ISD::SMAX:
H A DSelectionDAG.cpp3362 case ISD::SMAX: {
3365 bool IsMax = (Opcode == ISD::SMAX);
3368 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX))
3695 case ISD::SMAX: {
3698 bool IsMax = (Opcode == ISD::SMAX);
3701 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX))
4800 case ISD::SMAX: return C1.sge(C2) ? C1 : C2;
5197 case ISD::SMAX:
H A DLegalizeVectorOps.cpp443 case ISD::SMAX:
H A DLegalizeDAG.cpp3168 case ISD::SMAX:
3175 case ISD::SMAX: Pred = ISD::SETGT; break;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp345 setOperationAction(ISD::SMAX, Ty, Legal);
2010 return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
2022 return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp450 setOperationAction(ISD::SMAX, MVT::i16, Legal);
622 setOperationAction(ISD::SMAX, MVT::v2i16, Legal);
648 setOperationAction(ISD::SMAX, MVT::v4i16, Custom);
728 setTargetDAGCombine(ISD::SMAX);
4096 case ISD::SMAX:
9023 case ISD::SMAX:
9186 if (Opc == ISD::SMIN && Op0.getOpcode() == ISD::SMAX && Op0.hasOneUse()) {
9318 case ISD::SMAX:
10007 case ISD::SMAX:
H A DAMDGPUISelLowering.cpp348 setOperationAction(ISD::SMAX, MVT::i32, Legal);
2670 SDValue B = DAG.getNode(ISD::SMAX, DL, MVT::i32, OneSubExp, Zero);
/freebsd-11-stable/contrib/gcc/config/ia64/
H A Dia64.c1778 if (mode == V4HImode && (code == SMIN || code == SMAX))
1809 case SMAX:
5704 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp647 setOperationAction(ISD::SMAX, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp186 for (auto Op : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp903 setOperationAction(ISD::SMAX, VT, VT == MVT::v8i16 ? Legal : Custom);
1083 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
1084 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
1284 setOperationAction(ISD::SMAX, MVT::v4i64, Custom);
1300 setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom);
1559 setOperationAction(ISD::SMAX, VT, Legal);
1671 setOperationAction(ISD::SMAX, VT, Legal);
1816 setOperationAction(ISD::SMAX, VT, Legal);
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp191 setOperationAction(ISD::SMAX, VT, Legal);
928 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
2966 return DAG.getNode(ISD::SMAX, dl, Op.getValueType(),
12953 ReplaceReductionResults(N, Results, DAG, ISD::SMAX, AArch64ISD::SMAXV);

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