Searched refs:SINT_TO_FP (Results 1 - 25 of 29) sorted by relevance

12

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp243 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
246 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
248 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
250 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
252 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
254 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
256 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
258 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
260 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
262 { ISD::SINT_TO_FP, MV
[all...]
H A DARMISelLowering.cpp172 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
177 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
297 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
860 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
864 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
865 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
977 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
5467 case ISD::SINT_TO_FP:
5469 Opc = ISD::SINT_TO_FP;
5487 if (Op.getOpcode() == ISD::SINT_TO_FP)
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp326 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
327 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
328 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
334 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
335 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
336 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
342 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
343 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
348 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 },
349 { ISD::SINT_TO_FP, MV
[all...]
H A DAArch64ISelLowering.cpp296 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
297 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
298 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
635 setTargetDAGCombine(ISD::SINT_TO_FP);
733 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
742 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i8, MVT::v4i32);
744 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v8i8, MVT::v8i32);
747 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
749 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
753 setOperationAction(ISD::SINT_TO_FP, MV
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1303 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 },
1304 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
1305 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 },
1306 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 },
1307 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 },
1308 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 },
1359 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 },
1360 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 },
1361 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 },
1362 { ISD::SINT_TO_FP, MV
[all...]
H A DX86ISelLowering.cpp216 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
231 // Promote i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
233 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
237 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
240 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
244 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
804 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
979 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
981 setOperationAction(ISD::SINT_TO_FP, MV
[all...]
H A DX86IntrinsicsInfo.h919 X86_INTRINSIC_DATA(avx512_sitofp_round, INTR_TYPE_1OP, ISD::SINT_TO_FP, X86ISD::SINT_TO_FP_RND),
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h539 SINT_TO_FP, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp472 case ISD::SINT_TO_FP:
559 case ISD::SINT_TO_FP:
1335 // Make sure that the SINT_TO_FP and SRL instructions are available.
1336 if (((!IsStrict && TLI.getOperationAction(ISD::SINT_TO_FP, VT) ==
1399 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Node->getValueType(0), HI);
1401 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Node->getValueType(0), LO);
H A DLegalizeFloatTypes.cpp130 case ISD::SINT_TO_FP:
721 bool Signed = N->getOpcode() == ISD::SINT_TO_FP ||
1182 case ISD::SINT_TO_FP:
1561 bool isSigned = N->getOpcode() == ISD::SINT_TO_FP;
1564 // First do an SINT_TO_FP, whether the original was signed or unsigned.
1573 Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src);
1595 // Unsigned - fix up the SINT_TO_FP value just calculated.
2147 case ISD::SINT_TO_FP:
H A DLegalizeDAG.cpp1002 case ISD::SINT_TO_FP:
2347 Node->getOpcode() == ISD::SINT_TO_FP);
2420 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2430 Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2489 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2494 bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP ||
2499 unsigned SIntOp = IsStrict ? ISD::STRICT_SINT_TO_FP : ISD::SINT_TO_FP;
2511 // If the target supports SINT_TO_FP of this type, use it.
2968 case ISD::SINT_TO_FP:
4054 SDValue Exponent = DAG.getNode(ISD::SINT_TO_FP, SDLo
[all...]
H A DSelectionDAGDumper.cpp333 case ISD::SINT_TO_FP: return "sint_to_fp";
H A DLegalizeVectorTypes.cpp100 case ISD::SINT_TO_FP:
573 case ISD::SINT_TO_FP:
893 case ISD::SINT_TO_FP:
1953 case ISD::SINT_TO_FP:
2797 case ISD::SINT_TO_FP:
4217 case ISD::SINT_TO_FP:
H A DFastISel.cpp449 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg,
1909 return selectCast(I, ISD::SINT_TO_FP);
H A DSelectionDAG.cpp4132 case ISD::SINT_TO_FP:
4398 case ISD::SINT_TO_FP: {
4402 Opcode==ISD::SINT_TO_FP,
4537 case ISD::SINT_TO_FP:
4586 case ISD::SINT_TO_FP:
H A DTargetLowering.cpp6217 !isOperationLegalOrCustom(ISD::SINT_TO_FP, SrcVT) ||
6260 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Or);
6262 Fast = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Src);
H A DDAGCombiner.cpp1586 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
13034 if (N->getOpcode() == ISD::SINT_TO_FP && N0.getOpcode() == ISD::FP_TO_SINT &&
13059 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
13061 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
13063 if (!hasOperation(ISD::SINT_TO_FP, OpVT) &&
13123 // but SINT_TO_FP is legal on this target, try to convert.
13125 hasOperation(ISD::SINT_TO_FP, OpVT)) {
13126 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
13128 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
13157 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP)
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp220 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
221 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
227 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
394 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
401 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
532 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
539 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
553 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
559 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
729 setOperationAction(ISD::SINT_TO_FP, MV
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1510 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1512 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
3021 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this,
3371 case ISD::SINT_TO_FP:
3378 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp341 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
376 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
1148 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
1549 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
2493 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2555 return DAG.getNode(ISD::SINT_TO_FP, DL, DestVT, Ext);
H A DSIISelLowering.cpp505 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
510 setOperationAction(ISD::SINT_TO_FP, MVT::f16, Promote);
735 setTargetDAGCombine(ISD::SINT_TO_FP);
8602 case ISD::SINT_TO_FP:
8733 N0.getOpcode() == ISD::SINT_TO_FP)) {
10073 case ISD::SINT_TO_FP:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1600 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
1601 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
1602 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1626 case SIToFP: return ISD::SINT_TO_FP;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp403 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
404 setOperationAction(ISD::SINT_TO_FP, MVT::v2f64, Legal);
423 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
424 setOperationAction(ISD::SINT_TO_FP, MVT::v4f32, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp358 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
1876 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),

Completed in 844 milliseconds

12