Searched refs:SIGN_EXTEND (Results 1 - 25 of 79) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp182 {ISD::SIGN_EXTEND, MVT::i32, MVT::i16, 0},
184 {ISD::SIGN_EXTEND, MVT::i32, MVT::i8, 0},
186 {ISD::SIGN_EXTEND, MVT::i16, MVT::i8, 0},
188 {ISD::SIGN_EXTEND, MVT::i64, MVT::i32, 1},
190 {ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 1},
192 {ISD::SIGN_EXTEND, MVT::i64, MVT::i8, 1},
200 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0},
202 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 0},
204 {ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 0},
219 { ISD::SIGN_EXTEND, MV
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1282 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, member in class:ISD
1286 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, member in class:ISD
1287 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, member in class:ISD
1288 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, member in class:ISD
1289 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, member in class:ISD
1290 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, member in class:ISD
1291 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, member in class:ISD
1346 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 },
1348 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 },
1350 { ISD::SIGN_EXTEND, MV
[all...]
H A DX86ISelLowering.cpp807 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
1021 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1215 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1216 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1235 setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
1410 setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
1518 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1519 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1524 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i8, Custom);
1759 setOperationAction(ISD::SIGN_EXTEND, MV
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp308 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
310 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
312 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
314 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
316 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
318 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
320 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
322 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGAddressAnalysis.cpp248 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
260 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
H A DDAGCombiner.cpp1142 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1566 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1673 case ISD::SIGN_EXTEND:
2150 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() &&
2479 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
3211 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N1.getOperand(0));
4103 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
4104 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
4235 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
4236 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, D
[all...]
H A DLegalizeVectorTypes.cpp99 case ISD::SIGN_EXTEND:
395 return DAG.getNode(ISD::SIGN_EXTEND, DL, EltVT, Op);
569 case ISD::SIGN_EXTEND:
901 case ISD::SIGN_EXTEND:
1970 case ISD::SIGN_EXTEND:
2796 case ISD::SIGN_EXTEND:
3252 if (Opcode == ISD::SIGN_EXTEND)
3379 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, WidenSVT, Val);
3824 else if (N.getOpcode() == ISD::SIGN_EXTEND)
3866 Mask = DAG.getNode(ISD::SIGN_EXTEND, SDLo
[all...]
H A DFunctionLoweringInfo.cpp62 // prefer to use SIGN_EXTEND.
76 ExtendKind = ISD::SIGN_EXTEND;
/freebsd-11-stable/contrib/gcc/
H A Dsee.c695 if (GET_CODE (rhs) != SIGN_EXTEND && GET_CODE (rhs) != ZERO_EXTEND)
742 if (GET_CODE (rhs) != SIGN_EXTEND && GET_CODE (rhs) != ZERO_EXTEND)
752 if (GET_CODE (rhs) == SIGN_EXTEND)
753 return SIGN_EXTEND;
775 || (extension_code != SIGN_EXTEND && extension_code != ZERO_EXTEND))
779 if (extension_code == SIGN_EXTEND)
2464 gcc_assert (GET_CODE (rhs) == SIGN_EXTEND
2800 if (extension_code == SIGN_EXTEND)
2832 if (extension_code == SIGN_EXTEND)
3226 extension_code = SIGN_EXTEND;
[all...]
H A Dloop-iv.c660 case SIGN_EXTEND:
740 case SIGN_EXTEND:
936 case SIGN_EXTEND:
983 case SIGN_EXTEND:
1866 iv->extend = signed_p ? SIGN_EXTEND : ZERO_EXTEND;
1900 if (iv0->extend == SIGN_EXTEND
1901 || iv1->extend == SIGN_EXTEND)
1914 signed_p = iv0->extend == SIGN_EXTEND;
1916 signed_p = iv1->extend == SIGN_EXTEND;
1946 iv0->base = simplify_gen_unary (signed_p ? SIGN_EXTEND
[all...]
H A Dsimplify-rtx.c610 return simplify_gen_unary (SIGN_EXTEND, mode, temp, inner);
634 if ((GET_CODE (op) == SIGN_EXTEND
643 && (GET_CODE (XEXP (op, 0)) == SIGN_EXTEND
790 if (GET_CODE (op) == SIGN_EXTEND
806 if (GET_CODE (op) == SIGN_EXTEND)
811 case SIGN_EXTEND:
1078 case SIGN_EXTEND:
1217 case SIGN_EXTEND:
2227 if ((GET_CODE (op0) == SIGN_EXTEND
4696 || GET_CODE (op) == SIGN_EXTEND)
[all...]
H A Dregrename.c546 if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE
553 else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE
1471 if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE
1478 else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE
H A Drtlanal.c73 SIGN_EXTEND then while narrowing we also have to enforce the
3590 case SIGN_EXTEND:
3747 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
3969 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
4008 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
4062 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
4075 case SIGN_EXTEND:
4679 if (targetm.mode_rep_extended (i, wider) == SIGN_EXTEND
H A Dsched-vis.c283 case SIGN_EXTEND:
H A Dcombine.c1042 : SIGN_EXTEND),
2759 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2762 == SIGN_EXTEND)
2877 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3724 case SIGN_EXTEND:
4009 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4814 case SIGN_EXTEND:
5037 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5067 else if (GET_CODE (t) == SIGN_EXTEND
5084 extend_op = SIGN_EXTEND;
[all...]
H A Dpostreload.c293 case SIGN_EXTEND:
439 || GET_CODE (SET_SRC (set)) == SIGN_EXTEND)
H A Dalias.c935 case SIGN_EXTEND: /* used for NT/Alpha pointers */
1394 case SIGN_EXTEND: /* Used for Alpha/NT pointers */
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h524 /// SIGN_EXTEND - Used for integer types, replicating the sign bit
526 SIGN_EXTEND, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h127 return ISD::SIGN_EXTEND;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp102 setOperationAction(ISD::SIGN_EXTEND, T, Custom);
135 setOperationAction(ISD::SIGN_EXTEND, T, Custom);
761 ValV = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, ValV);
1553 case ISD::SIGN_EXTEND:
1571 case ISD::SIGN_EXTEND: return LowerHvxSignExt(Op, DAG);
H A DHexagonISelDAGToDAG.cpp1452 case ISD::SIGN_EXTEND:
1455 EVT T = Opc == ISD::SIGN_EXTEND
1510 case ISD::SIGN_EXTEND:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp2527 case ISD::SIGN_EXTEND:
2548 N->getOpcode() == ISD::SIGN_EXTEND) &&
2562 N->getOpcode() == ISD::SIGN_EXTEND ?
2572 NumSextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 1 : 0;
2573 NumZextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 0 : 1;
2745 Input.getOperand(0).getOpcode() == ISD::SIGN_EXTEND))
3580 if (CompareUse->getOpcode() != ISD::SIGN_EXTEND &&
3652 case ISD::SIGN_EXTEND:
4259 (TrueResVal == 1 && FalseRes.getOpcode() != ISD::SIGN_EXTEND) ||
5524 N->getOpcode() != ISD::SIGN_EXTEND
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp99 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
351 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
837 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
/freebsd-11-stable/contrib/gcc/config/s390/
H A Ds390.c591 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
602 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
613 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
2167 else if (GET_CODE (left) == SIGN_EXTEND)
2182 else if (GET_CODE (left) == SIGN_EXTEND)
2189 if (GET_CODE (left) == SIGN_EXTEND
2190 && GET_CODE (right) == SIGN_EXTEND)
2279 case SIGN_EXTEND:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp667 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1382 case ISD::SIGN_EXTEND: {

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