Searched refs:SCALAR_TO_VECTOR (Results 1 - 19 of 19) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h423 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a
429 SCALAR_TO_VECTOR, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp58 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
262 ISD::SCALAR_TO_VECTOR, DL, OtherVT, SDValue(ScalarNode, OtherNo));
655 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op);
672 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
738 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Res);
768 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
783 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
838 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
1489 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
2694 case ISD::SCALAR_TO_VECTOR
[all...]
H A DSelectionDAGDumper.cpp285 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector";
H A DLegalizeDAG.cpp400 // SCALAR_TO_VECTOR requires that the type of the value being inserted
406 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
1833 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1914 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1941 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1996 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1999 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
3025 case ISD::SCALAR_TO_VECTOR:
4660 case ISD::SCALAR_TO_VECTOR: {
H A DLegalizeIntegerTypes.cpp103 case ISD::SCALAR_TO_VECTOR:
1274 case ISD::SCALAR_TO_VECTOR:
1513 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
3776 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
4294 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
H A DDAGCombiner.cpp1611 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N);
4460 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
4462 if ((HandOpcode == ISD::BITCAST || HandOpcode == ISD::SCALAR_TO_VECTOR) &&
17082 if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) {
17084 // SCALAR_TO_VECTOR may truncate the inserted element and the
17130 BCSrc.getOpcode() == ISD::SCALAR_TO_VECTOR) {
17268 } else if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
18140 if (!LegalOperations && Scalar.getOpcode() == ISD::SCALAR_TO_VECTOR &&
18174 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), NVT, Scalar);
18781 // BUILD_VECTOR or SCALAR_TO_VECTOR int
[all...]
H A DTargetLowering.cpp857 case ISD::SCALAR_TO_VECTOR: {
2186 case ISD::SCALAR_TO_VECTOR: {
H A DSelectionDAG.cpp2673 case ISD::SCALAR_TO_VECTOR: {
4328 // FIXME: Add support for SCALAR_TO_VECTOR as well.
4728 case ISD::SCALAR_TO_VECTOR:
4734 "Illegal SCALAR_TO_VECTOR node!");
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp940 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1349 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1619 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1788 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i16, Custom);
1789 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v64i8, Custom);
1985 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
2729 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2961 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v1i1, ValReturned);
3289 ? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val)
3957 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, d
[all...]
H A DX86ISelDAGToDAG.cpp954 SDValue Op0 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT,
956 SDValue Op1 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT,
2406 // Need to make sure that the SCALAR_TO_VECTOR and load are both only used
2409 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR && N.getNode()->hasOneUse()) {
H A DX86FastISel.cpp2652 // The following SCALAR_TO_VECTOR will be expanded into a VMOVDI2PDIrr.
2653 InputReg = fastEmit_r(MVT::i32, MVT::v4i32, ISD::SCALAR_TO_VECTOR,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp436 SDValue TiedIn = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), VT, Lo);
716 assert(N->getOpcode() == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
788 case ISD::SCALAR_TO_VECTOR:
2787 case ISD::SCALAR_TO_VECTOR:
H A DSIISelLowering.cpp274 case ISD::SCALAR_TO_VECTOR:
303 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
304 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
536 case ISD::SCALAR_TO_VECTOR:
738 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
5485 AddrLo = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VectorVT,
10087 case ISD::SCALAR_TO_VECTOR: {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp370 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
486 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
487 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
4643 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value);
4905 // Detect SCALAR_TO_VECTOR conversions.
4906 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op))
4930 if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
5075 if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
5191 case ISD::SCALAR_TO_VECTOR:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp683 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
770 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
771 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
785 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
788 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
792 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
793 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
794 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
795 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
1011 setOperationAction(ISD::SCALAR_TO_VECTOR, MV
[all...]
H A DPPCISelDAGToDAG.cpp5006 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp7231 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
7946 // SCALAR_TO_VECTOR, except for when we have a single-element constant vector
7950 "SCALAR_TO_VECTOR node\n");
7951 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
8117 // Use SCALAR_TO_VECTOR for lane zero to
8129 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op0);
12261 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
12263 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp326 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
416 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
5523 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
5525 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
7248 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
7967 // Test if V1 is a SCALAR_TO_VECTOR.
7968 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
7971 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
7972 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1490 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR,

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