Searched refs:Rs (Results 1 - 25 of 32) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp109 // P0 = cmp.eq(Rs,#u2)
121 // Rd = Rs
162 // Rd=Rs ; jump #r9:2
200 MCOperand Rs, Rt; local
222 Rs = L.getOperand(1);
228 CompoundInsn->addOperand(Rs);
235 Rs = L.getOperand(1);
241 CompoundInsn->addOperand(Rs);
248 Rs = L.getOperand(1);
254 CompoundInsn->addOperand(Rs);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp636 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
639 Rs)));
641 Rs)));
650 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
653 Rs)));
655 Rs)));
675 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
680 if (Rs >= Rt) {
683 } else if (Rs != 0 && Rs < R
705 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
748 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
778 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
819 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
858 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
900 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
945 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
987 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
1036 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
1092 InsnType Rs = fieldFromInstruction(Insn, 21, 5); local
1134 InsnType Rs = fieldFromInstruction(Insn, 21, 5); local
1152 InsnType Rs = fieldFromInstruction(Insn, 21, 5); local
2561 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
2610 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
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/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_mips.cpp40 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs,
43 return (Opcode | Rs << 21 | Rt << 16 | Imm);
47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd,
49 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
H A Dxray_mips64.cpp41 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs,
44 return (Opcode | Rs << 21 | Rt << 16 | Imm);
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd,
50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
/freebsd-11-stable/contrib/mdocml/
H A Dmdoc.h149 struct mdoc_rs Rs; member in union:mdoc_data
H A Dmdoc_markdown.c192 { md_cond_body, md_pre_Rs, NULL, NULL, NULL }, /* Rs */
1545 if (n->parent->tok == MDOC_Rs && n->parent->norm->Rs.quote_T)
1557 if (n->parent->tok == MDOC_Rs && n->parent->norm->Rs.quote_T)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp279 // In memw(Rs+##V), the ##V could be replaced by a register Rt to
280 // form the rr mode: memw(Rt+Rs<<0). In such case, however, the
282 // another instruction memw(Rs+##V+4), it would need a different Rt.
283 // Now, if Rt was initialized as "##V+Rs<<0", both of these
290 // Include shifting the Rs to account for the ur addressing mode:
291 // ##Val + Rs << S
292 // ##Val - Rs
293 Register Rs; member in struct:__anon2229::HexagonConstExtenders::ExtExpr
298 ExtExpr(Register RS, bool NG, unsigned SH) : Rs(RS), S(SH), Neg(NG) {}
301 return Rs
446 HCE::Register Rs; member in struct:__anon2229::PrintRegister
1504 Register Rs = ExtI.second.Rs; // Only one reg allowed now. local
1783 Register Rs = MI.getOperand(IsSub ? 3 : 2); local
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H A DHexagonSplitDouble.cpp103 void collectIndRegsForLoop(const MachineLoop *L, USet &Rs);
147 const USet &Rs = I.second; local
148 if (Rs.find(Reg) != Rs.end())
375 Register Rs = MI->getOperand(1).getReg(); local
377 return profit(Rs) + profit(Rt);
477 USet &Rs) {
561 Rs.insert(DP.begin(), End);
562 Rs.insert(CmpR1);
563 Rs
476 collectIndRegsForLoop(const MachineLoop *L, USet &Rs) argument
584 USet Rs; local
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H A DHexagonGenInsert.cpp129 RegisterSet &insert(const RegisterSet &Rs) { argument
130 return static_cast<RegisterSet&>(BitVector::operator|=(Rs));
132 RegisterSet &remove(const RegisterSet &Rs) { argument
133 return static_cast<RegisterSet&>(BitVector::reset(Rs));
156 bool includes(const RegisterSet &Rs) const {
158 return !Rs.BitVector::test(*this);
160 bool intersects(const RegisterSet &Rs) const {
161 return BitVector::anyCommon(Rs);
1233 void stats(const RegisterSet &Rs, unsigned &Size, unsigned &Zero,
1270 void IFOrdering::stats(const RegisterSet &Rs, unsigne
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H A DHexagonAsmPrinter.cpp409 MCOperand &Rs = Inst.getOperand(1); local
410 assert(Rs.isReg() && "Expected register and none was found");
411 unsigned Reg = RI->getEncodingValue(Rs.getReg());
416 Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI));
486 // if ("#u5==0") Assembler mapped to: "Rd=Rs"; else Rd=asr(Rs,#u5-1):rnd
537 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
H A DHexagonBitSimplify.cpp109 RegisterSet &insert(const RegisterSet &Rs) { argument
110 return static_cast<RegisterSet&>(BitVector::operator|=(Rs));
112 RegisterSet &remove(const RegisterSet &Rs) { argument
113 return static_cast<RegisterSet&>(BitVector::reset(Rs));
136 bool includes(const RegisterSet &Rs) const {
138 return !Rs.BitVector::test(*this);
140 bool intersects(const RegisterSet &Rs) const {
141 return BitVector::anyCommon(Rs);
1758 BitTracker::RegisterRef &Rs, BitTracker::RegisterRef &Rt);
1882 // set the inputs Rs an
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H A DHexagonFrameLowering.cpp143 // Rd = PS_alloca Rs, A
146 // Rs - minimum size (the actual allocated can be larger to accommodate
2391 // Rd = alloca Rs, #A
2393 // If Rs and Rd are different registers, use this sequence:
2394 // Rd = sub(r29, Rs)
2395 // r29 = sub(r29, Rs)
2400 // Rd = sub(r29, Rs)
2407 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); local
2409 // Rd = sub(r29, Rs)
2412 .addReg(Rs);
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H A DHexagonBitTracker.cpp296 auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt,
298 uint16_t I = Odd, Ws = Rs.width();
300 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW));
303 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW));
465 // 32-bit negation is done by "Rd = A2_subri 0, Rs"
650 // Result: S2_asr_i_r_rnd Rs, u5-1
702 // Res.uw[1] = Rs[bx+1:], Res.uw[0] = Rs[0:bx]
H A DHexagonISelLowering.cpp2561 SDValue Rs[8];
2567 Rs[i] = DAG.getSelect(dl, MVT::i32, Ops[i/Rep], S, Z);
2569 for (ArrayRef<SDValue> A(Rs); A.size() != 1; A = A.drop_back(A.size()/2)) {
2571 Rs[i] = DAG.getNode(ISD::OR, dl, MVT::i32, Rs[2*i], Rs[2*i+1]);
2574 return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {Rs[0]}, DAG);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) { argument
155 switch (Rs) {
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); local
184 return DecodeSrcAddrMode(Rs, As);
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); local
190 return DecodeSrcAddrMode(Rs, As);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp138 Register Rs = TailAdd.getOperand(1).getReg(); local
140 Register Reg = Rs == GAReg ? Rt : Rs;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1377 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
1618 MCOperand &Rs = Inst.getOperand(2); local
1628 TmpInst.addOperand(Rs);
1638 MCOperand &Rs = Inst.getOperand(2); local
1648 TmpInst.addOperand(Rs);
1658 MCOperand &Rs = Inst.getOperand(2); local
1668 TmpInst.addOperand(Rs);
1681 MCOperand &Rs = Inst.getOperand(1); local
1698 TmpInst.addOperand(Rs);
1711 if (Value == 0) { // convert to $Rd = $Rs
1714 MCOperand &Rs = Inst.getOperand(1); local
1724 MCOperand &Rs = Inst.getOperand(1); local
1766 MCOperand &Rs = Inst.getOperand(1); local
1783 MCOperand &Rs = Inst.getOperand(1); local
1912 MCOperand &Rs = Inst.getOperand(1); local
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/freebsd-11-stable/contrib/llvm-project/clang/lib/Tooling/Core/
H A DReplacement.cpp221 Replacements Rs(R);
230 Rs.getReplacementInChangedCode(Replace));
234 auto MergeShiftedReplaces = Rs.merge(ReplacesShiftedByRs);
/freebsd-11-stable/contrib/binutils/gas/config/
H A Dtc-arm.c4243 (LSL|LSR|ASL|ASR|ROR) Rs
7268 UMULL RdLo, RdHi, Rm, Rs
7269 SMULL RdLo, RdHi, Rm, Rs
7270 UMLAL RdLo, RdHi, Rm, Rs
7271 SMLAL RdLo, RdHi, Rm, Rs. */
7465 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
7489 SMLAxy{cond} Rd,Rm,Rs,Rn
7490 SMLAWy{cond} Rd,Rm,Rs,Rn
7503 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7520 SMULxy{cond} Rd,Rm,Rs
8444 int Rd, Rs, Rn; local
8669 int Rd, Rs, Rn; local
8752 int Rd, Rs, Rn; local
10125 int Rd, Rs; local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp1293 unsigned Rs = fieldFromInstruction(insn, 16, 5); local
1305 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1329 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1341 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1350 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
/freebsd-11-stable/contrib/ntp/sntp/ag-tpl/0-old/
H A DMdoc.pm100 The C<CODE> is called after a Rs/Re block is done. With a hash reference as a
200 def_macro('.Rs', sub { () } );
/freebsd-11-stable/contrib/ntp/sntp/ag-tpl/
H A DMdoc.pm127 The C<CODE> is called after a Rs/Re block is done. With a hash reference as a
227 def_macro('.Rs', sub { () } );
/freebsd-11-stable/contrib/openpam/misc/
H A Dgendoc.pl539 $mdoc .= ".Rs
651 .Rs
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp4086 unsigned Rs = Inst.getOperand(0).getReg(); local
4089 if (RI->isSubRegisterEq(Rt, Rs) ||
4090 (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
4099 unsigned Rs = Inst.getOperand(0).getReg(); local
4103 if (RI->isSubRegisterEq(Rt1, Rs) || RI->isSubRegisterEq(Rt2, Rs) ||
4104 (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp1501 // shifted. The second is Rs, the amount to shift by, and the third specifies
1507 // {11-8} = Rs
1520 unsigned Rs = MO1.getReg();
1521 if (Rs) {
1538 // Encode the shift operation Rs.
1539 // Encode Rs bit[11:8].
1541 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);

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