/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | AllocationOrder.cpp | 31 const RegisterClassInfo &RegClassInfo, 36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); 29 AllocationOrder(unsigned VirtReg, const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo, const LiveRegMatrix *Matrix) argument
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H A D | AllocationOrder.h | 42 /// @param RegClassInfo Information about reserved and allocatable registers. 45 const RegisterClassInfo &RegClassInfo,
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H A D | CriticalAntiDepBreaker.h | 41 const RegisterClassInfo &RegClassInfo; member in class:llvm::CriticalAntiDepBreaker
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H A D | RegAllocBase.h | 69 RegisterClassInfo RegClassInfo; member in class:llvm::RegAllocBase
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H A D | RegAllocBase.cpp | 66 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction()); 137 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
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H A D | BreakFalseDeps.cpp | 38 RegisterClassInfo RegClassInfo; member in class:llvm::BreakFalseDeps 144 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); 271 RegClassInfo.runOnMachineFunction(mf);
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H A D | AggressiveAntiDepBreaker.h | 122 const RegisterClassInfo &RegClassInfo; member in class:llvm::AggressiveAntiDepBreaker
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H A D | PostRASchedulerList.cpp | 82 RegisterClassInfo RegClassInfo; member in class:__anon1785::PostRAScheduler 291 RegClassInfo.runOnMachineFunction(Fn); 314 SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode,
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H A D | RegAllocGreedy.cpp | 810 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix); 922 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) < 923 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg))); 1095 unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg); 1128 unsigned MinCost = RegClassInfo.getMinCost(RC); 1138 OrderLimit = RegClassInfo.getLastCostChange(RC); 1153 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) 1690 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); 2023 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); 2090 if (!RegClassInfo [all...] |
H A D | RegAllocBasic.cpp | 262 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
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H A D | CriticalAntiDepBreaker.cpp | 48 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), 407 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
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H A D | RegAllocFast.cpp | 75 RegisterClassInfo RegClassInfo; member in class:__anon1790::RegAllocFast 716 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); 763 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); 1302 RegClassInfo.runOnMachineFunction(MF);
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H A D | TargetRegisterInfo.cpp | 47 const RegClassInfo *const RCIs,
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H A D | MachineScheduler.cpp | 143 RegClassInfo = new RegisterClassInfo(); 147 delete RegClassInfo; 387 RegClassInfo->runOnMachineFunction(*MF); 1001 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, 1003 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd, 1055 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i); 1085 unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID); 1268 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd, 2760 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
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H A D | AggressiveAntiDepBreaker.cpp | 130 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) { 632 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
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H A D | RegisterCoalescer.cpp | 134 RegisterClassInfo RegClassInfo; member in class:__anon1797::RegisterCoalescer 1953 if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC())) 3884 RegClassInfo.runOnMachineFunction(fn);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIPreAllocateWWMRegs.cpp | 44 RegisterClassInfo RegClassInfo; member in class:__anon2130::SIPreAllocateWWMRegs 107 for (unsigned PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { 177 RegClassInfo.runOnMachineFunction(MF);
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H A D | GCNSchedStrategy.cpp | 44 SGPRExcessLimit = Context->RegClassInfo 46 VGPRExcessLimit = Context->RegClassInfo
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H A D | SIMachineScheduler.h | 451 RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false);
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | MachineScheduler.h | 127 RegisterClassInfo *RegClassInfo; member in struct:llvm::MachineSchedContext 383 RegisterClassInfo *RegClassInfo; member in class:llvm::ScheduleDAGMILive 427 RegClassInfo(C->RegClassInfo), RPTracker(RegPressure),
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H A D | TargetRegisterInfo.h | 232 struct RegClassInfo { struct in class:llvm::TargetRegisterInfo 244 const RegClassInfo *const RCInfos; 254 const RegClassInfo *const RCIs, 653 const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const {
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H A D | MachinePipeliner.h | 67 RegisterClassInfo RegClassInfo; member in class:llvm::MachinePipeliner 122 const RegisterClassInfo &RegClassInfo; member in class:llvm::SwingSchedulerDAG 203 RegClassInfo(rci), II_setByPragma(II), Topo(SUnits, &ExitSU) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonMachineScheduler.h | 99 RegisterClassInfo *getRegClassInfo() { return RegClassInfo; }
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 109 RegisterClassInfo RegClassInfo; member in struct:__anon2164::ARMLoadStoreOpt 583 RegClassInfo.runOnMachineFunction(*MF); 587 for (unsigned Reg : RegClassInfo.getOrder(&RegClass))
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
H A D | MIParser.cpp | 306 auto RegClassInfo = Names2RegClasses.find(Name); local 307 if (RegClassInfo == Names2RegClasses.end()) 309 return RegClassInfo->getValue();
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