Searched refs:RegClassInfo (Results 1 - 25 of 26) sorted by relevance

12

/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DAllocationOrder.cpp31 const RegisterClassInfo &RegClassInfo,
36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
29 AllocationOrder(unsigned VirtReg, const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo, const LiveRegMatrix *Matrix) argument
H A DAllocationOrder.h42 /// @param RegClassInfo Information about reserved and allocatable registers.
45 const RegisterClassInfo &RegClassInfo,
H A DCriticalAntiDepBreaker.h41 const RegisterClassInfo &RegClassInfo; member in class:llvm::CriticalAntiDepBreaker
H A DRegAllocBase.h69 RegisterClassInfo RegClassInfo; member in class:llvm::RegAllocBase
H A DRegAllocBase.cpp66 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
137 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
H A DBreakFalseDeps.cpp38 RegisterClassInfo RegClassInfo; member in class:llvm::BreakFalseDeps
144 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
271 RegClassInfo.runOnMachineFunction(mf);
H A DAggressiveAntiDepBreaker.h122 const RegisterClassInfo &RegClassInfo; member in class:llvm::AggressiveAntiDepBreaker
H A DPostRASchedulerList.cpp82 RegisterClassInfo RegClassInfo; member in class:__anon1785::PostRAScheduler
291 RegClassInfo.runOnMachineFunction(Fn);
314 SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode,
H A DRegAllocGreedy.cpp810 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
922 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) <
923 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
1095 unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg);
1128 unsigned MinCost = RegClassInfo.getMinCost(RC);
1138 OrderLimit = RegClassInfo.getLastCostChange(RC);
1153 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI)
1690 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
2023 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
2090 if (!RegClassInfo
[all...]
H A DRegAllocBasic.cpp262 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
H A DCriticalAntiDepBreaker.cpp48 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI),
407 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
H A DRegAllocFast.cpp75 RegisterClassInfo RegClassInfo; member in class:__anon1790::RegAllocFast
716 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC);
763 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC);
1302 RegClassInfo.runOnMachineFunction(MF);
H A DTargetRegisterInfo.cpp47 const RegClassInfo *const RCIs,
H A DMachineScheduler.cpp143 RegClassInfo = new RegisterClassInfo();
147 delete RegClassInfo;
387 RegClassInfo->runOnMachineFunction(*MF);
1001 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin,
1003 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd,
1055 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
1085 unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID);
1268 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd,
2760 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
H A DAggressiveAntiDepBreaker.cpp130 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) {
632 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
H A DRegisterCoalescer.cpp134 RegisterClassInfo RegClassInfo; member in class:__anon1797::RegisterCoalescer
1953 if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC()))
3884 RegClassInfo.runOnMachineFunction(fn);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPreAllocateWWMRegs.cpp44 RegisterClassInfo RegClassInfo; member in class:__anon2130::SIPreAllocateWWMRegs
107 for (unsigned PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) {
177 RegClassInfo.runOnMachineFunction(MF);
H A DGCNSchedStrategy.cpp44 SGPRExcessLimit = Context->RegClassInfo
46 VGPRExcessLimit = Context->RegClassInfo
H A DSIMachineScheduler.h451 RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineScheduler.h127 RegisterClassInfo *RegClassInfo; member in struct:llvm::MachineSchedContext
383 RegisterClassInfo *RegClassInfo; member in class:llvm::ScheduleDAGMILive
427 RegClassInfo(C->RegClassInfo), RPTracker(RegPressure),
H A DTargetRegisterInfo.h232 struct RegClassInfo { struct in class:llvm::TargetRegisterInfo
244 const RegClassInfo *const RCInfos;
254 const RegClassInfo *const RCIs,
653 const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const {
H A DMachinePipeliner.h67 RegisterClassInfo RegClassInfo; member in class:llvm::MachinePipeliner
122 const RegisterClassInfo &RegClassInfo; member in class:llvm::SwingSchedulerDAG
203 RegClassInfo(rci), II_setByPragma(II), Topo(SUnits, &ExitSU) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.h99 RegisterClassInfo *getRegClassInfo() { return RegClassInfo; }
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp109 RegisterClassInfo RegClassInfo; member in struct:__anon2164::ARMLoadStoreOpt
583 RegClassInfo.runOnMachineFunction(*MF);
587 for (unsigned Reg : RegClassInfo.getOrder(&RegClass))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp306 auto RegClassInfo = Names2RegClasses.find(Name); local
307 if (RegClassInfo == Names2RegClasses.end())
309 return RegClassInfo->getValue();

Completed in 295 milliseconds

12