/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/ |
H A D | AVRInstPrinter.cpp | 107 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || 108 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) || 109 (MOI.RegClass == AVR::ZREGRegClassID);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | Utils.cpp | 33 const TargetRegisterClass &RegClass) { 34 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) 35 return MRI.createVirtualRegister(&RegClass); 44 const TargetRegisterClass &RegClass, const MachineOperand &RegMO, 50 unsigned ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); 79 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); local 88 if (RegClass && !RegClass->isAllocatable()) 89 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); 91 if (!RegClass) { 30 constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, unsigned Reg, const TargetRegisterClass &RegClass) argument 40 constrainOperandRegClass( const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | RegisterClassInfo.h | 47 std::unique_ptr<RCInfo[]> RegClass; member in class:llvm::RegisterClassInfo 74 const RCInfo &RCI = RegClass[RC->getID()];
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H A D | RegisterScavenging.h | 166 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj, argument 168 return scavengeRegister(RegClass, MBBI, SPAdj, AllowSpill);
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H A D | RDFRegisters.h | 136 const TargetRegisterClass *RegClass = nullptr; member in struct:llvm::rdf::PhysicalRegisterInfo::RegInfo
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyPeephole.cpp | 97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); local 98 switch (RegClass->getID()) { 120 Register NewReg = MRI.createVirtualRegister(RegClass);
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H A D | WebAssemblyRegStackify.cpp | 105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); local 106 if (RegClass == &WebAssembly::I32RegClass) { 109 } else if (RegClass == &WebAssembly::I64RegClass) { 112 } else if (RegClass == &WebAssembly::F32RegClass) { 117 } else if (RegClass == &WebAssembly::F64RegClass) { 122 } else if (RegClass == &WebAssembly::V128RegClass) { 609 const auto *RegClass = MRI.getRegClass(Reg); local 610 Register TeeReg = MRI.createVirtualRegister(RegClass); 611 Register DefReg = MRI.createVirtualRegister(RegClass); 614 TII->get(getTeeOpcode(RegClass)), TeeRe [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | Utils.h | 48 const TargetRegisterClass &RegClass); 51 /// TargetRegisterClass passed as an argument (RegClass). 63 const TargetRegisterClass &RegClass, 70 /// This is equivalent to constrainOperandRegClass(..., RegClass, ...) 71 /// with RegClass obtained from the MCInstrDesc. The debug location of \p
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | RDFRegisters.cpp | 36 if (RI.RegClass != nullptr && !BadRC[R]) { 37 if (RC->LaneMask != RI.RegClass->LaneMask) { 39 RI.RegClass = nullptr; 42 RI.RegClass = RC; 66 if (const TargetRegisterClass *RC = RegInfos[F].RegClass) 171 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; 232 LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask
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H A D | RegisterClassInfo.cpp | 50 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); 92 RCInfo &RCI = RegClass[RC->getID()];
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H A D | MachineRegisterInfo.cpp | 158 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, argument 160 assert(RegClass && "Cannot create register without RegClass!"); 161 assert(RegClass->isAllocatable() && 162 "Virtual register RegClass must be allocatable."); 166 VRegInfo[Reg].first = RegClass;
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H A D | RenameIndependentSubregs.cpp | 134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); local 142 Register NewVReg = MRI->createVirtualRegister(RegClass);
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H A D | TargetInstrInfo.cpp | 52 short RegClass = MCID.OpInfo[OpNum].RegClass; local 54 return TRI->getPointerRegClass(MF, RegClass); 57 if (RegClass < 0) 61 return TRI->getRegClass(RegClass);
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
H A D | MCInstrDesc.h | 81 int16_t RegClass; member in class:llvm::MCOperandInfo
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | Thumb2InstrInfo.cpp | 483 const TargetRegisterClass *RegClass = 664 RegClass->contains(FrameReg))) { 668 if (!MRI->constrainRegClass(FrameReg, RegClass)) 705 RegClass->contains(FrameReg));
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H A D | ARMBaseRegisterInfo.cpp | 814 const TargetRegisterClass *RegClass = local 818 (Register::isVirtualRegister(FrameReg) || RegClass->contains(FrameReg))) 822 ScratchReg = MF.getRegInfo().createVirtualRegister(RegClass);
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/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | RISCVCompressInstEmitter.cpp | 120 bool validateRegister(Record *Reg, Record *RegClass); 140 bool RISCVCompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) { argument 142 assert(RegClass->isSubClassOf("RegisterClass") && "RegClass record should be" 144 CodeGenRegisterClass RC = Target.getRegisterClass(RegClass);
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H A D | CodeGenRegisters.cpp | 1534 for (auto &RegClass : RegClasses) { 1537 if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr) 1547 RegClass.LaneMask = LaneMask; 1595 for (auto &RegClass : RegBank.getRegClasses()) { 1596 if (!RegClass.Allocatable) 1599 const CodeGenRegister::Vec &Regs = RegClass.getMembers(); 1869 // Create a RegUnitSet for each RegClass that contains all units in the class 1874 // RegisterInfoEmitter will map each RegClass to its RegUnitClass and any 1879 // Compute a unique RegUnitSet for each RegClass. 2088 // Compute a unique set of RegUnitSets. One for each RegClass an [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64AsmPrinter.cpp | 706 const TargetRegisterClass *RegClass; local 708 RegClass = &AArch64::ZPRRegClass; 710 RegClass = &AArch64::PPRRegClass; 712 RegClass = &AArch64::FPR128RegClass; 717 return printAsmRegInClass(MO, RegClass, AltName, O);
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H A D | AArch64LoadStoreOptimizer.cpp | 1023 "Unexpected RegClass"); 1286 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); 1288 if (!RegClass || !MF.getRegInfo().tracksLiveness()) 1416 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); 1417 for (const MCPhysReg &PR : *RegClass) { 1428 << TRI->getRegClassName(RegClass) << "\n");
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
H A D | AMDGPUDisassembler.cpp | 119 #define DECODE_OPERAND_REG(RegClass) \ 120 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 541 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 564 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.cpp | 763 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg); local 764 if (RegClass == &AMDGPU::SReg_32RegClass || 765 RegClass == &AMDGPU::SGPR_32RegClass || 766 RegClass == &AMDGPU::SReg_32_XM0RegClass || 767 RegClass == &AMDGPU::SReg_32_XM0_XEXECRegClass) { 773 if (RegClass == &AMDGPU::SReg_64RegClass || 774 RegClass == &AMDGPU::SGPR_64RegClass || 775 RegClass == &AMDGPU::SReg_64_XEXECRegClass) { 781 if (RegClass == &AMDGPU::VGPR_32RegClass) { 786 if (RegClass [all...] |
H A D | AMDGPUMachineCFGStructurizer.cpp | 1934 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg); 1935 Register TrueBBReg = MRI->createVirtualRegister(RegClass); 1936 Register FalseBBReg = MRI->createVirtualRegister(RegClass); 2001 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); 2002 Register NextDestReg = MRI->createVirtualRegister(RegClass); 2061 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); 2062 Register PHIDestReg = MRI->createVirtualRegister(RegClass); 2063 Register IfSourceReg = MRI->createVirtualRegister(RegClass); 2176 const TargetRegisterClass *RegClass = 2178 Register NewBackedgeReg = MRI->createVirtualRegister(RegClass); [all...] |
H A D | SIInstrInfo.h | 812 if (OpInfo.RegClass == -1) { 818 return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8; 1036 return RI.getRegClass(TID.OpInfo[OpNum].RegClass);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FrameLowering.cpp | 586 const TargetRegisterClass *RegClass = &X86::GR64RegClass; 588 : MRI.createVirtualRegister(RegClass), 590 : MRI.createVirtualRegister(RegClass), 592 : MRI.createVirtualRegister(RegClass), 594 : MRI.createVirtualRegister(RegClass), 596 : MRI.createVirtualRegister(RegClass), 598 : MRI.createVirtualRegister(RegClass), 600 : MRI.createVirtualRegister(RegClass), 602 : MRI.createVirtualRegister(RegClass), 604 : MRI.createVirtualRegister(RegClass); [all...] |