Searched refs:RegClass (Results 1 - 25 of 55) sorted by relevance

123

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRInstPrinter.cpp107 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) ||
108 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) ||
109 (MOI.RegClass == AVR::ZREGRegClassID);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp33 const TargetRegisterClass &RegClass) {
34 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))
35 return MRI.createVirtualRegister(&RegClass);
44 const TargetRegisterClass &RegClass, const MachineOperand &RegMO,
50 unsigned ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
79 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); local
88 if (RegClass && !RegClass->isAllocatable())
89 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI);
91 if (!RegClass) {
30 constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, unsigned Reg, const TargetRegisterClass &RegClass) argument
40 constrainOperandRegClass( const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h47 std::unique_ptr<RCInfo[]> RegClass; member in class:llvm::RegisterClassInfo
74 const RCInfo &RCI = RegClass[RC->getID()];
H A DRegisterScavenging.h166 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj, argument
168 return scavengeRegister(RegClass, MBBI, SPAdj, AllowSpill);
H A DRDFRegisters.h136 const TargetRegisterClass *RegClass = nullptr; member in struct:llvm::rdf::PhysicalRegisterInfo::RegInfo
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); local
98 switch (RegClass->getID()) {
120 Register NewReg = MRI.createVirtualRegister(RegClass);
H A DWebAssemblyRegStackify.cpp105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); local
106 if (RegClass == &WebAssembly::I32RegClass) {
109 } else if (RegClass == &WebAssembly::I64RegClass) {
112 } else if (RegClass == &WebAssembly::F32RegClass) {
117 } else if (RegClass == &WebAssembly::F64RegClass) {
122 } else if (RegClass == &WebAssembly::V128RegClass) {
609 const auto *RegClass = MRI.getRegClass(Reg); local
610 Register TeeReg = MRI.createVirtualRegister(RegClass);
611 Register DefReg = MRI.createVirtualRegister(RegClass);
614 TII->get(getTeeOpcode(RegClass)), TeeRe
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h48 const TargetRegisterClass &RegClass);
51 /// TargetRegisterClass passed as an argument (RegClass).
63 const TargetRegisterClass &RegClass,
70 /// This is equivalent to constrainOperandRegClass(..., RegClass, ...)
71 /// with RegClass obtained from the MCInstrDesc. The debug location of \p
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DRDFRegisters.cpp36 if (RI.RegClass != nullptr && !BadRC[R]) {
37 if (RC->LaneMask != RI.RegClass->LaneMask) {
39 RI.RegClass = nullptr;
42 RI.RegClass = RC;
66 if (const TargetRegisterClass *RC = RegInfos[F].RegClass)
171 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass;
232 LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask
H A DRegisterClassInfo.cpp50 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
92 RCInfo &RCI = RegClass[RC->getID()];
H A DMachineRegisterInfo.cpp158 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, argument
160 assert(RegClass && "Cannot create register without RegClass!");
161 assert(RegClass->isAllocatable() &&
162 "Virtual register RegClass must be allocatable.");
166 VRegInfo[Reg].first = RegClass;
H A DRenameIndependentSubregs.cpp134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); local
142 Register NewVReg = MRI->createVirtualRegister(RegClass);
H A DTargetInstrInfo.cpp52 short RegClass = MCID.OpInfo[OpNum].RegClass; local
54 return TRI->getPointerRegClass(MF, RegClass);
57 if (RegClass < 0)
61 return TRI->getRegClass(RegClass);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrDesc.h81 int16_t RegClass; member in class:llvm::MCOperandInfo
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp483 const TargetRegisterClass *RegClass =
664 RegClass->contains(FrameReg))) {
668 if (!MRI->constrainRegClass(FrameReg, RegClass))
705 RegClass->contains(FrameReg));
H A DARMBaseRegisterInfo.cpp814 const TargetRegisterClass *RegClass = local
818 (Register::isVirtualRegister(FrameReg) || RegClass->contains(FrameReg)))
822 ScratchReg = MF.getRegInfo().createVirtualRegister(RegClass);
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp120 bool validateRegister(Record *Reg, Record *RegClass);
140 bool RISCVCompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) { argument
142 assert(RegClass->isSubClassOf("RegisterClass") && "RegClass record should be"
144 CodeGenRegisterClass RC = Target.getRegisterClass(RegClass);
H A DCodeGenRegisters.cpp1534 for (auto &RegClass : RegClasses) {
1537 if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr)
1547 RegClass.LaneMask = LaneMask;
1595 for (auto &RegClass : RegBank.getRegClasses()) {
1596 if (!RegClass.Allocatable)
1599 const CodeGenRegister::Vec &Regs = RegClass.getMembers();
1869 // Create a RegUnitSet for each RegClass that contains all units in the class
1874 // RegisterInfoEmitter will map each RegClass to its RegUnitClass and any
1879 // Compute a unique RegUnitSet for each RegClass.
2088 // Compute a unique set of RegUnitSets. One for each RegClass an
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp706 const TargetRegisterClass *RegClass; local
708 RegClass = &AArch64::ZPRRegClass;
710 RegClass = &AArch64::PPRRegClass;
712 RegClass = &AArch64::FPR128RegClass;
717 return printAsmRegInClass(MO, RegClass, AltName, O);
H A DAArch64LoadStoreOptimizer.cpp1023 "Unexpected RegClass");
1286 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg());
1288 if (!RegClass || !MF.getRegInfo().tracksLiveness())
1416 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg());
1417 for (const MCPhysReg &PR : *RegClass) {
1428 << TRI->getRegClassName(RegClass) << "\n");
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp119 #define DECODE_OPERAND_REG(RegClass) \
120 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
541 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
564 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp763 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg); local
764 if (RegClass == &AMDGPU::SReg_32RegClass ||
765 RegClass == &AMDGPU::SGPR_32RegClass ||
766 RegClass == &AMDGPU::SReg_32_XM0RegClass ||
767 RegClass == &AMDGPU::SReg_32_XM0_XEXECRegClass) {
773 if (RegClass == &AMDGPU::SReg_64RegClass ||
774 RegClass == &AMDGPU::SGPR_64RegClass ||
775 RegClass == &AMDGPU::SReg_64_XEXECRegClass) {
781 if (RegClass == &AMDGPU::VGPR_32RegClass) {
786 if (RegClass
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H A DAMDGPUMachineCFGStructurizer.cpp1934 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg);
1935 Register TrueBBReg = MRI->createVirtualRegister(RegClass);
1936 Register FalseBBReg = MRI->createVirtualRegister(RegClass);
2001 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg);
2002 Register NextDestReg = MRI->createVirtualRegister(RegClass);
2061 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
2062 Register PHIDestReg = MRI->createVirtualRegister(RegClass);
2063 Register IfSourceReg = MRI->createVirtualRegister(RegClass);
2176 const TargetRegisterClass *RegClass =
2178 Register NewBackedgeReg = MRI->createVirtualRegister(RegClass);
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H A DSIInstrInfo.h812 if (OpInfo.RegClass == -1) {
818 return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
1036 return RI.getRegClass(TID.OpInfo[OpNum].RegClass);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp586 const TargetRegisterClass *RegClass = &X86::GR64RegClass;
588 : MRI.createVirtualRegister(RegClass),
590 : MRI.createVirtualRegister(RegClass),
592 : MRI.createVirtualRegister(RegClass),
594 : MRI.createVirtualRegister(RegClass),
596 : MRI.createVirtualRegister(RegClass),
598 : MRI.createVirtualRegister(RegClass),
600 : MRI.createVirtualRegister(RegClass),
602 : MRI.createVirtualRegister(RegClass),
604 : MRI.createVirtualRegister(RegClass);
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