Target/AMDGPU/SIInstrInfo.cpp

763   const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);
764   if (RegClass == &AMDGPU::SReg_32RegClass ||
765       RegClass == &AMDGPU::SGPR_32RegClass ||
766       RegClass == &AMDGPU::SReg_32_XM0RegClass ||
767       RegClass == &AMDGPU::SReg_32_XM0_XEXECRegClass) {
773   if (RegClass == &AMDGPU::SReg_64RegClass ||
774       RegClass == &AMDGPU::SGPR_64RegClass ||
775       RegClass == &AMDGPU::SReg_64_XEXECRegClass) {
781   if (RegClass == &AMDGPU::VGPR_32RegClass) {
786   if (RegClass == &AMDGPU::VReg_64RegClass) {
794   if (RI.isSGPRClass(RegClass)) {
795     if (RI.getRegSizeInBits(*RegClass) > 32) {
804   ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RegClass, EltSize);
2943   if (OpInfo.RegClass < 0)
3250     int RegClass = Desc.OpInfo[i].RegClass;
3296     if (RegClass != -1) {
3301       const TargetRegisterClass *RC = RI.getRegClass(RegClass);
3821       Desc.OpInfo[OpNo].RegClass == -1) {
3829   unsigned RCID = Desc.OpInfo[OpNo].RegClass;
3840   unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass;
3933   const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass);
3966       OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
4680     unsigned RsrcRC = get(MI.getOpcode()).OpInfo[RsrcIdx].RegClass;
5823     const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
6278   const auto RCID = MI.getDesc().OpInfo[Idx].RegClass;