/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64AsmBackend.cpp | 633 unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true); variable 650 Reg1 = getXRegFromWReg(Reg1); 653 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && 656 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && 659 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && 662 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && 665 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && 669 Reg1 = getDRegFromBReg(Reg1); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsAsmPrinter.h | 94 unsigned Reg1, unsigned Reg2); 97 unsigned Reg1, unsigned Reg2, unsigned Reg3); 100 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
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H A D | MipsTargetStreamer.h | 127 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc, 129 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2, 131 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, 133 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, 135 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm, 137 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
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H A D | MipsAsmPrinter.cpp | 875 unsigned Opcode, unsigned Reg1, 884 unsigned Temp = Reg1; 885 Reg1 = Reg2; 889 I.addOperand(MCOperand::createReg(Reg1)); 895 unsigned Opcode, unsigned Reg1, 899 I.addOperand(MCOperand::createReg(Reg1)); 906 unsigned MovOpc, unsigned Reg1, 910 unsigned temp = Reg1; 911 Reg1 = Reg2; 914 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg 874 EmitInstrRegReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg1, unsigned Reg2) argument 894 EmitInstrRegRegReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg1, unsigned Reg2, unsigned Reg3) argument 905 EmitMovFPIntPair(const MCSubtargetInfo &STI, unsigned MovOpc, unsigned Reg1, unsigned Reg2, unsigned FPReg1, unsigned FPReg2, bool LE) argument [all...] |
H A D | Mips16InstrInfo.h | 120 unsigned Reg1, unsigned Reg2) const;
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H A D | Mips16InstrInfo.cpp | 278 unsigned Reg1, unsigned Reg2) const { 287 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1); 291 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1); 292 MIB3.addReg(Reg1); 296 MIB4.addReg(Reg1, RegState::Kill); 275 adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Reg1, unsigned Reg2) const argument
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H A D | MicroMipsSizeReduction.cpp | 377 // Returns true if the registers Reg1 and Reg2 are consecutive 378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { argument 387 if (Registers[i] == Reg1) { 406 Register Reg1 = MI1->getOperand(0).getReg(); 409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); 478 Register Reg1 = MI1->getOperand(1).getReg(); 481 if (Reg1 != Reg2)
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H A D | MipsSEFrameLowering.cpp | 465 unsigned Reg1 = local 469 std::swap(Reg0, Reg1); 477 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); 482 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; local 485 std::swap(Reg0, Reg1); 493 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64FrameLowering.cpp | 524 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); local 527 .addImm(Reg1) 537 Register Reg1 = MBBI->getOperand(2).getReg(); local 538 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) 545 .addImm(RegInfo->getSEHRegNum(Reg1)) 575 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); local 578 .addImm(Reg1) 586 Register Reg1 = MBBI->getOperand(1).getReg(); local 587 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) 594 .addImm(RegInfo->getSEHRegNum(Reg1)) 1873 invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2, bool NeedsWinCFI) argument 1896 invalidateRegisterPairing(unsigned Reg1, unsigned Reg2, bool UsesWinAAPCS, bool NeedsWinCFI, bool NeedsFrameRecord) argument 1912 unsigned Reg1 = AArch64::NoRegister; member in struct:__anon92::RegPairInfo 2137 unsigned Reg1 = RPI.Reg1; local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/ |
H A D | SystemZAsmParser.cpp | 419 bool parseAddress(bool &HaveReg1, Register &Reg1, 834 // Parse a memory operand into Reg1, Reg2, Disp, and Length. 835 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, argument 853 if (parseRegister(Reg1)) 900 Register Reg1, Reg2; local 904 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length)) 909 // If we have Reg1, it must be an address register. 911 if (parseAddressRegister(Reg1)) 913 Base = Regs[Reg1.Num]; 926 // If we have Reg1, i 1214 Register Reg1, Reg2; local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
H A D | MCRegisterInfo.h | 77 bool contains(MCRegister Reg1, MCRegister Reg2) const { argument 78 return contains(Reg1) && contains(Reg2); 740 uint16_t Reg1 = 0; member in class:llvm::MCRegUnitRootIterator 748 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; 764 Reg0 = Reg1; 765 Reg1 = 0;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsTargetStreamer.cpp | 190 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, argument 192 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); 205 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, argument 211 TmpInst.addOperand(MCOperand::createReg(Reg1)); 217 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, argument 220 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); 223 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, argument 229 TmpInst.addOperand(MCOperand::createReg(Reg1)); 236 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, argument 239 emitRRX(Opcode, Reg0, Reg1, MCOperan 242 emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, const MCSubtargetInfo *STI) argument [all...] |
H A D | MipsMCCodeEmitter.cpp | 99 unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1); local 103 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!"); 104 if (Reg0 < Reg1) 107 if (Reg0 >= Reg1) 111 if (Reg1 >= Reg0)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | AggressiveAntiDepBreaker.h | 103 // Union Reg1's and Reg2's groups to form a new group. 105 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
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H A D | TargetInstrInfo.cpp | 175 Register Reg1 = MI.getOperand(Idx1).getReg(); local 188 bool Reg1IsRenamable = Register::isPhysicalRegister(Reg1) 196 if (HasDef && Reg0 == Reg1 && 204 Reg0 = Reg1; 221 CommutedMI->getOperand(Idx2).setReg(Reg1); 233 if (Register::isPhysicalRegister(Reg1))
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | GCNRegBankReassign.cpp | 187 unsigned Reg1, 402 unsigned Reg1, 415 if (Def->modifiesRegister(Reg1, TRI)) 540 unsigned Reg1 = OperandMasks[I].Reg; 549 LLVM_DEBUG(dbgs() << "Conflicting operands: " << printReg(Reg1, SubReg1) << 552 unsigned Weight = getOperandGatherWeight(MI, Reg1, Reg2, StallCycles); 557 unsigned FreeBanks1 = getFreeBanks(Reg1, SubReg1, Mask1, UsedBanks); 560 Candidates.push(Candidate(&MI, Reg1, FreeBanks1, Weight
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 165 unsigned Reg1, bool isKill1, 167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) 164 addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) argument
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H A D | X86AvoidStoreForwardingBlocks.cpp | 395 Register Reg1 = MRI->createVirtualRegister( local 399 Reg1) 425 .addReg(Reg1)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 225 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); local 249 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); 264 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetRegisterInfo.h | 98 bool contains(unsigned Reg1, unsigned Reg2) const { argument 101 if (!Register::isPhysicalRegister(Reg1) || 104 return MC->contains(Reg1, Reg2);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 82 const DebugLoc &DL, unsigned Reg1, 449 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { 455 .addReg(Reg1) 447 createRegSequence( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const DebugLoc &DL, unsigned Reg1, unsigned Reg2) argument
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H A D | Thumb2SizeReduction.cpp | 747 Register Reg1 = MI->getOperand(1).getReg(); local 752 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) 758 if (Reg1 != Reg0) 765 } else if (Reg0 != Reg1) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMInstPrinter.cpp | 1438 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); 1442 printRegName(O, Reg1); 1451 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); 1455 printRegName(O, Reg1); 1506 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); 1510 printRegName(O, Reg1); 1553 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); 1557 printRegName(O, Reg1);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
H A D | HexagonAsmParser.cpp | 1382 StringRef Reg1(R1); 1383 MO.setReg(matchRegister(Reg1)); 1397 StringRef Reg1(R1); 1398 MO.setReg(matchRegister(Reg1)); 1413 StringRef Reg1(R1); 1414 MO.setReg(matchRegister(Reg1)); 1745 StringRef Reg1(R1); 1746 Rss.setReg(matchRegister(Reg1)); 1889 StringRef Reg1(R1); 1890 Rss.setReg(matchRegister(Reg1)); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 668 unsigned Reg1 = Reg; local 673 .addReg(Reg1, RegState::Kill) 713 unsigned Reg1 = Reg; local 719 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 817 unsigned Reg1 = Reg; local 822 .addReg(Reg1, RegState::Kill)
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