Searched refs:RSP (Results 1 - 16 of 16) sorted by relevance
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86LoadValueInjectionRetHardening.cpp | 77 UnclobberableGR64s.set(X86::RSP); // can't clobber stack pointer
119 // RSP to assert that RSP points to a valid page. The write to RSP is
124 X86::RSP, false, 0) member in class:X86
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| H A D | X86FrameLowering.cpp | 187 if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP &&
312 // Load new SP from the top of the stack into RSP.
540 // We need to exit with RSP modified by this amount and execute suitable
542 // All stack probing must be done without modifying RSP.
547 // CopyReg = RSP
560 // RSP = RSP - RAX
635 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
639 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
652 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP);
[all...] |
| H A D | X86RegisterInfo.cpp | 64 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
533 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP))
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| H A D | X86IndirectThunks.cpp | 273 const Register SPReg = Is64Bit ? X86::RSP : X86::ESP;
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| H A D | X86SpeculativeLoadHardening.cpp | 1917 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::OR64rr), X86::RSP)
1918 .addReg(X86::RSP)
1935 .addReg(X86::RSP);
1964 } else if (BaseMO.getReg() == X86::RSP) {
1967 // explicit RSP register as the base.
1969 "Explicit RSP access with dynamic index!");
1971 dbgs() << " Cannot harden base of explicit RSP offset in a load!");
2392 // pointers canonical) and merge it into RSP. This will allow the caller to
2521 .addReg(/*Base*/ X86::RSP)
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| H A D | X86FixupLEAs.cpp | 372 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP))
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| H A D | X86InstrInfo.cpp | 927 // LEA can't handle RSP.
8152 if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
8153 MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
8154 MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
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| H A D | X86ISelDAGToDAG.cpp | 396 (RegNode->getReg() == X86::RSP))
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| H A D | X86ISelLowering.cpp | 23575 // Return EntryEBP + ParentFrameOffset for x64. This adjusts from RSP after
25119 .Case("rsp", X86::RSP)
[all...] |
| /freebsd-11-stable/sys/amd64/amd64/ |
| H A D | bpf_jit_machdep.c | 205 MOVrq(RSP, RBP);
206 SUBib(BPF_MEMWORDS * sizeof(uint32_t), RSP); local
399 MOVobd(RSP, RSI, EAX);
404 MOVobd(RSP, RSI, EDX);
414 MOVomd(EAX, RSP, RSI);
419 MOVomd(EDX, RSP, RSI);
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| H A D | bpf_jit_machdep.h | 44 #define RSP 4 macro
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 163 {codeview::RegisterId::RSP, X86::RSP},
352 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
613 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
641 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
678 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
714 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
750 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
751 return X86::RSP;
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| H A D | X86MCCodeEmitter.cpp | 502 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
568 assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP &&
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/DebugInfo/CodeView/ |
| H A D | SymbolRecordMapping.cpp | 511 case EncodedFramePtrReg::StackPtr: return RegisterId::RSP;
546 case RegisterId::RSP:
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86DisassemblerDecoder.h | 195 ENTRY(RSP) \
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 1073 IndexReg == X86::ESP || IndexReg == X86::RSP) {
1974 if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP &&
1975 (IndexReg == X86::ESP || IndexReg == X86::RSP))
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