| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterClassInfo.cpp | 92 RCInfo &RCI = RegClass[RC->getID()]; local
98 if (!RCI.Order)
99 RCI.Order.reset(new MCPhysReg[NumRegs]);
125 RCI.Order[N++] = PhysReg;
129 RCI.NumRegs = N + CSRAlias.size();
130 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
138 RCI.Order[N++] = PhysReg;
143 if (StressRA && RCI.NumRegs > StressRA)
144 RCI.NumRegs = StressRA;
149 if (Super != RC && getNumAllocatableRegs(Super) > RCI
[all...] |
| H A D | CriticalAntiDepBreaker.h | 74 CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI);
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| H A D | TargetRegisterInfo.cpp | 270 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
271 if (RCI.getSubReg() == Idx)
274 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
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| H A D | AggressiveAntiDepBreaker.h | 133 const RegisterClassInfo &RCI,
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| H A D | ShrinkWrap.cpp | 112 RegisterClassInfo RCI; member in class:__anon1825::ShrinkWrap
189 RCI.runOnMachineFunction(MF);
292 RCI.getLastCalleeSavedAlias(PhysReg);
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| H A D | PostRASchedulerList.cpp | 208 const RegisterClassInfo &RCI,
225 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) :
227 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : nullptr));
206 SchedulePostRATDList( MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA, const RegisterClassInfo &RCI, TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs) argument
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| H A D | RegisterPressure.cpp | 273 RCI = rci;
961 const RegisterClassInfo *RCI,
971 unsigned Limit = RCI->getRegPressureSetLimit(i);
1105 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI,
1171 unsigned Limit = RCI->getRegPressureSetLimit(PSetID);
1351 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI,
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| H A D | CriticalAntiDepBreaker.cpp | 45 const RegisterClassInfo &RCI)
48 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI),
44 CriticalAntiDepBreaker(MachineFunction &MFi, const RegisterClassInfo &RCI) argument
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| H A D | RegAllocGreedy.cpp | 164 RegisterClassInfo RCI; member in class:__anon1792::RAGreedy
2067 const RegisterClassInfo &RCI) {
2075 return RCI.getNumAllocatableRegs(ConstrainedRC);
2107 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC);
2117 TRI, RCI)) {
3222 RCI.runOnMachineFunction(mf);
2064 getNumAllocatableRegsForConstraints( const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, const RegisterClassInfo &RCI) argument
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| H A D | AggressiveAntiDepBreaker.cpp | 126 MachineFunction &MFi, const RegisterClassInfo &RCI,
130 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) {
125 AggressiveAntiDepBreaker( MachineFunction &MFi, const RegisterClassInfo &RCI, TargetSubtargetInfo::RegClassVector &CriticalPathRCs) argument
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| H A D | TargetLoweringBase.cpp | 1122 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1123 SuperRegRC.setBitsInMask(RCI.getMask());
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 74 const RCInfo &RCI = RegClass[RC->getID()]; local
75 if (Tag != RCI.Tag)
77 return RCI;
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| H A D | RegisterPressure.h | 361 const RegisterClassInfo *RCI = nullptr;
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | ConstantHoisting.cpp | 315 for (auto const &RCI : ConstInfo.RebasedConstants)
316 for (auto const &U : RCI.Uses)
851 for (auto const &RCI : ConstInfo.RebasedConstants) {
852 for (auto const &U : RCI.Uses) {
860 ToBeRebased.push_back(RebasedUse(RCI.Offset, RCI.Ty, U));
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | CGSCCPassManager.h | 767 for (auto RCI = CG.postorder_ref_scc_begin(),
769 RCI != RCE;) {
783 RCWorklist.insert(&*RCI++);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64A57FPLoadBalancing.cpp | 112 RegisterClassInfo RCI; member in class:__anon2015::AArch64A57FPLoadBalancing
321 RCI.runOnMachineFunction(F);
519 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));
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