Searched refs:OrigReg (Results 1 - 9 of 9) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTailDuplicator.h98 void addSSAUpdateEntry(unsigned OrigReg, unsigned NewReg,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp555 Register OrigReg = U.getReg(); local
556 U.setReg(Substs[OrigReg]);
560 ToErase.push_back(OrigReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTailDuplicator.cpp329 void TailDuplicator::addSSAUpdateEntry(unsigned OrigReg, unsigned NewReg, argument
332 SSAUpdateVals.find(OrigReg);
338 SSAUpdateVals.insert(std::make_pair(OrigReg, Vals));
339 SSAUpdateVRs.push_back(OrigReg);
H A DInlineSpiller.cpp1169 /// i.e., there should be a living sibling of OrigReg at the insert point.
1173 unsigned OrigReg = OrigLI.reg; local
1179 SmallSetVector<unsigned, 16> &Siblings = Virt2SiblingsMap[OrigReg];
1240 // to the OrigReg. It means the def instruction should dominate all the spills
H A DSplitKit.cpp341 unsigned OrigReg = VRM.getOriginal(CurLI->reg); local
342 const LiveInterval &Orig = LIS.getInterval(OrigReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBankInfo.cpp468 Register OrigReg = MO.getReg(); local
470 LLVM_DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr));
476 LLT OrigTy = MRI.getType(OrigReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp4078 const SCEV *OrigReg; member in struct:__anon2717::WorkItem
4081 : LUIdx(LI), Imm(I), OrigReg(R) {}
4091 OS << "in formulae referencing " << *OrigReg << " in use " << LUIdx
4140 const SCEV *OrigReg = J->second; local
4143 const SmallBitVector &UsedByIndices = RegUses.getUsedByIndices(OrigReg);
4145 if (!isa<SCEVConstant>(OrigReg) &&
4147 LLVM_DEBUG(dbgs() << "Skipping cross-use reuse for " << *OrigReg
4174 WorkItems.push_back(WorkItem(LUIdx, Imm, OrigReg));
4189 const SCEV *OrigReg = WI.OrigReg; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRegBankReassign.cpp658 Register OrigReg = VRM->getPhys(C.Reg);
678 LRM->assign(LI, OrigReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1346 unsigned OrigReg = OrigOp.Mem.BaseReg; local
1352 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) {
1357 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg))
1359 else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg))
1361 else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg))
1371 if (FinalReg != OrigReg) {

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