Searched refs:Orders (Results 1 - 8 of 8) sorted by relevance
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.cpp | 733 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
749 Orders.push_back({DVOrder, DbgMI});
762 SmallVectorImpl<std::pair<unsigned, MachineInstr *>> &Orders,
768 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0);
778 Orders.push_back({Order, NewInsn});
783 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
831 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
911 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen, NewInsn);
923 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders, Seen,
940 llvm::stable_sort(Orders, less_firs
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| H A D | FastISel.cpp | 255 Orders[&I] = Order++;
282 OrderMap.Orders.erase(&LocalMI);
289 if (OrderMap.Orders.empty())
296 auto I = OrderMap.Orders.find(&UseInst);
297 assert(I != OrderMap.Orders.end() &&
326 unsigned UseOrder = OrderMap.Orders[&DbgVal];
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | ConstantHoisting.cpp | 247 // in Orders.
249 SmallVector<BasicBlock *, 16> Orders; local
250 Orders.push_back(Entry);
251 while (Idx != Orders.size()) {
252 BasicBlock *Node = Orders[Idx++];
255 Orders.push_back(ChildDomNode->getBlock());
259 // Visit Orders in bottom-up order.
266 InsertPtsMap.reserve(Orders.size() + 1);
267 for (auto RIt = Orders.rbegin(); RIt != Orders
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | InlineSpiller.cpp | 128 SmallVectorImpl<MachineDomTreeNode *> &Orders,
1229 SmallVectorImpl<MachineDomTreeNode *> &Orders,
1286 // in Orders. Orders will be used for hoisting in runHoistSpills.
1288 Orders.push_back(MDT.getBase().getNode(Root));
1290 MachineDomTreeNode *Node = Orders[idx++];
1296 Orders.push_back(Child);
1298 } while (idx != Orders.size());
1299 assert(Orders.size() == WorkSet.size() &&
1300 "Orders hav
1227 getVisitOrders( MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills, SmallVectorImpl<MachineDomTreeNode *> &Orders, SmallVectorImpl<MachineInstr *> &SpillsToRm, DenseMap<MachineDomTreeNode *, unsigned> &SpillsToKeep, DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill) argument
1320 SmallVector<MachineDomTreeNode *, 32> Orders; local
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| /freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 295 std::vector<SmallVector<Record*, 16>> Orders; member in class:llvm::CodeGenRegisterClass
427 return Orders[No];
431 unsigned getNumOrders() const { return Orders.size(); }
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| H A D | CodeGenRegisters.cpp | 761 Orders.resize(1 + AltOrders->size());
766 Orders[0].push_back((*Elements)[i]);
778 Orders[1 + i].append(Order.begin(), Order.end());
854 Orders.resize(Super.Orders.size());
855 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i)
856 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j)
857 if (contains(RegBank.getReg(Super.Orders[i][j])))
858 Orders[i].push_back(Super.Orders[
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | FastISel.h | 576 DenseMap<MachineInstr *, unsigned> Orders; member in struct:llvm::FastISel::InstOrderMap
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| /freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 3061 llvm::AtomicOrdering Orders[5] = {
3075 Ptr, NewVal, Orders[i]);
3127 llvm::AtomicOrdering Orders[3] = {
3137 Store->setOrdering(Orders[i]);
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