Searched refs:NewSrc (Results 1 - 7 of 7) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DPeepholeOptimizer.cpp1196 RegSubRegPair NewSrc = getNewSource(MRI, TII, TrackPair, RewriteMap, local
1198 if (Src.Reg == NewSrc.Reg || NewSrc.Reg == 0)
1202 if (CpyRewriter->RewriteCurrentSource(NewSrc.Reg, NewSrc.SubReg)) {
1203 // We may have extended the live-range of NewSrc, account for that.
1204 MRI->clearKillFlags(NewSrc.Reg);
1229 RegSubRegPair NewSrc = getNewSource(MRI, TII, Def, RewriteMap); local
1238 .addReg(NewSrc.Reg, 0, NewSrc
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.h224 unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
H A DX86InstrInfo.cpp704 unsigned Opc, bool AllowSP, Register &NewSrc,
720 NewSrc = SrcReg;
724 if (Register::isVirtualRegister(NewSrc) &&
725 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
737 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
743 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
746 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
703 classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned Opc, bool AllowSP, Register &NewSrc, bool &isKill, MachineOperand &ImplicitOp, LiveVariables *LV) const argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstructionCombining.cpp1883 // put NewSrc at same location as %src
1885 auto *NewSrc = cast<GetElementPtrInst>( local
1887 NewSrc->setIsInBounds(Src->isInBounds());
1888 auto *NewGEP = GetElementPtrInst::Create(GEPEltType, NewSrc, {SO1});
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenDAGPatterns.cpp4268 TreePatternNodePtr NewSrc = P.SrcPattern->clone();
4270 if (!NewSrc->setDefaultMode(Mode) || !NewDst->setDefaultMode(Mode)) {
4277 PatternsToMatch.emplace_back(P.getSrcRecord(), Preds, std::move(NewSrc),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1754 SDValue NewSrc = local
1757 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
H A DTargetLowering.cpp1795 if (SDValue NewSrc = SimplifyMultipleUseDemandedBits(
1797 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, NewSrc));

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