/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyPeephole.cpp | 59 /// If desirable, rewrite NewReg to a drop register. 60 static bool maybeRewriteToDrop(unsigned OldReg, unsigned NewReg, argument 64 if (OldReg == NewReg) { 66 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); local 67 MO.setReg(NewReg); 69 MFI.stackifyVReg(NewReg); 120 Register NewReg = MRI.createVirtualRegister(RegClass); local 121 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(CopyLocalOpc), NewReg) 123 MO.setReg(NewReg); 124 MFI.stackifyVReg(NewReg); 168 Register NewReg = Op2.getReg(); local [all...] |
H A D | WebAssemblyDebugValueManager.h | 32 void clone(MachineInstr *Insert, unsigned NewReg);
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H A D | WebAssemblyDebugValueManager.cpp | 38 unsigned NewReg) { 43 Clone->getOperand(0).setReg(NewReg); 37 clone(MachineInstr *Insert, unsigned NewReg) argument
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H A D | WebAssemblyExplicitLocals.cpp | 248 Register NewReg = MRI.createVirtualRegister(RC); local 250 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Opc), NewReg) 252 MI.getOperand(2).setReg(NewReg); 253 MFI.stackifyVReg(NewReg); 279 Register NewReg = MRI.createVirtualRegister(RC); local 290 .addReg(NewReg); 301 .addReg(NewReg); 303 MI.getOperand(0).setReg(NewReg); 308 MFI.stackifyVReg(NewReg); 354 Register NewReg local [all...] |
H A D | WebAssemblyRegStackify.cpp | 502 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg)); local 503 Def->getOperand(0).setReg(NewReg); 504 Op.setReg(NewReg); 507 LIS.createAndComputeVirtRegInterval(NewReg); 515 MFI.stackifyVReg(NewReg); 517 DefDIs.updateReg(NewReg); 538 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg)); local 539 TII->reMaterialize(MBB, Insert, NewReg, 0, Def, *TRI); 540 Op.setReg(NewReg); 543 LIS.createAndComputeVirtRegInterval(NewReg); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | AntiDepBreaker.h | 58 /// other machine instruction to use NewReg. 59 void UpdateDbgValue(MachineInstr &MI, unsigned OldReg, unsigned NewReg) { argument 62 MI.getOperand(0).setReg(NewReg); 66 /// breaker's update of ParentMI to use NewReg. 68 unsigned OldReg, unsigned NewReg) { 76 UpdateDbgValue(*DbgMI, OldReg, NewReg); 67 UpdateDbgValues(const DbgValueVector &DbgValues, MachineInstr *ParentMI, unsigned OldReg, unsigned NewReg) argument
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H A D | CriticalAntiDepBreaker.cpp | 346 // be replaced by NewReg. Return true if any of their parent instructions may 351 // the two-address instruction also defines NewReg, as may happen with 355 // both NewReg and AntiDepReg covers it. 359 unsigned NewReg) { 364 // operands, in case they may be assigned to NewReg. In this case antidep 369 // Handle cases in which this instruction defines NewReg. 374 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg)) 378 CheckOper.getReg() != NewReg) 381 // Don't allow the instruction to define NewReg and AntiDepReg. 387 // NewReg 357 isNewRegClobberedByRefs(RegRefIter RegRefBegin, RegRefIter RegRefEnd, unsigned NewReg) argument 409 unsigned NewReg = Order[i]; local [all...] |
H A D | AggressiveAntiDepBreaker.cpp | 662 unsigned NewReg = 0; 664 NewReg = NewSuperReg; 668 NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx); 671 LLVM_DEBUG(dbgs() << " " << printReg(NewReg, TRI)); 673 // Check if Reg can be renamed to NewReg. 674 if (!RenameRegisterMap[Reg].test(NewReg)) { 679 // If NewReg is dead and NewReg's most recent def is not before 680 // Regs's kill, it's safe to replace Reg with NewReg. We 681 // must also check all aliases of NewReg, becaus [all...] |
H A D | CriticalAntiDepBreaker.h | 101 unsigned NewReg);
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H A D | MachineCSE.cpp | 600 Register NewReg = CSMI->getOperand(i).getReg(); local 609 if (MO.isImplicit() && !MO.isDead() && OldReg == NewReg) 612 if (OldReg == NewReg) { 618 Register::isVirtualRegister(NewReg) && 621 if (!isProfitableToCSE(NewReg, OldReg, CSMI->getParent(), MI)) { 630 if (!MRI->constrainRegAttrs(NewReg, OldReg)) { 637 CSEPairs.push_back(std::make_pair(OldReg, NewReg)); 645 unsigned NewReg = CSEPair.second; local 647 MachineInstr *Def = MRI->getUniqueVRegDef(NewReg); 649 Def->clearRegisterDeads(NewReg); 829 Register NewReg = MRI->cloneVirtualRegister(VReg); local [all...] |
H A D | ModuloSchedule.cpp | 405 unsigned NewReg = VRMap[PrevStage][LoopVal]; local 407 InitVal, NewReg); 420 unsigned NewReg = 0; local 520 NewReg = PhiOp2; 527 NewReg = VRMap[ReuseStage - np][LoopVal]; 530 Def, NewReg); 532 VRMap[CurStageNum - np][Def] = NewReg; 533 PhiOp2 = NewReg; 538 replaceRegUsesAfterLoop(Def, NewReg, BB, MRI, LIS); 549 NewReg 665 Register NewReg = MRI.createVirtualRegister(RC); local 1034 Register NewReg = MRI.createVirtualRegister(RC); local 1136 rewriteScheduledInstr( MachineBasicBlock *BB, InstrMapTy &InstrMap, unsigned CurStageNum, unsigned PhiNum, MachineInstr *Phi, unsigned OldReg, unsigned NewReg, unsigned PrevReg) argument [all...] |
H A D | TailDuplicator.cpp | 329 void TailDuplicator::addSSAUpdateEntry(unsigned OrigReg, unsigned NewReg, argument 334 LI->second.push_back(std::make_pair(BB, NewReg)); 337 Vals.push_back(std::make_pair(BB, NewReg)); 399 Register NewReg = MRI->createVirtualRegister(RC); local 400 MO.setReg(NewReg); 401 LocalVRMap.insert(std::make_pair(Reg, RegSubRegPair(NewReg, 0))); 403 addSSAUpdateEntry(Reg, NewReg, PredBB); 443 Register NewReg = MRI->createVirtualRegister(NewRC); local 445 TII->get(TargetOpcode::COPY), NewReg) 448 LocalVRMap.insert(std::make_pair(Reg, RegSubRegPair(NewReg, [all...] |
H A D | LiveDebugValues.cpp | 246 /// setting the register location to NewReg. 250 unsigned NewReg) { 255 VL.Loc.RegNo = NewReg; 260 /// be NewReg. 262 unsigned NewReg) { 265 VL.Loc.RegNo = NewReg; 521 unsigned NewReg = 0); 853 /// new VarLoc. If \p NewReg is different than default zero value then the 859 unsigned NewReg) { 879 assert(NewReg 247 CreateEntryCopyBackupLoc(const MachineInstr &MI, LexicalScopes &LS, const DIExpression *EntryExpr, unsigned NewReg) argument 261 CreateCopyLoc(const MachineInstr &MI, LexicalScopes &LS, unsigned NewReg) argument 856 insertTransferDebugPair( MachineInstr &MI, OpenRangesSet &OpenRanges, TransferMap &Transfers, VarLocMap &VarLocIDs, unsigned OldVarID, TransferKind Kind, unsigned NewReg) argument [all...] |
H A D | PeepholeOptimizer.cpp | 823 /// Rewrite the current source with \p NewReg and \p NewSubReg if possible. 825 virtual bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) = 0; 853 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override { 857 MOSrc.setReg(NewReg); 898 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override { 942 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override { 947 MO.setReg(NewReg); 989 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override { 994 CopyLike.getOperand(CurrentSrcIdx).setReg(NewReg); variable 1067 bool RewriteCurrentSource(unsigned NewReg, unsigne [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64DeadRegisterDefinitionsPass.cpp | 161 unsigned NewReg; local 166 NewReg = AArch64::WZR; 168 NewReg = AArch64::XZR; 174 MO.setReg(NewReg);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | Localizer.cpp | 159 Register NewReg = MRI->createGenericVirtualRegister(MRI->getType(Reg)); local 160 MRI->setRegClassOrRegBank(NewReg, MRI->getRegClassOrRegBank(Reg)); 161 LocalizedMI->getOperand(0).setReg(NewReg); 163 MBBWithLocalDef.insert(std::make_pair(MBBAndReg, NewReg)).first;
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H A D | CallLowering.cpp | 327 Register NewReg = 329 Handler.assignValueToReg(NewReg, VA.getLocReg(), VA); 341 auto Unmerge = MIRBuilder.buildUnmerge({OrigTy, OrigTy}, {NewReg}); 344 MIRBuilder.buildTrunc(ArgReg, {NewReg}).getReg(0); 475 Register NewReg = MRI.createGenericVirtualRegister(LocTy); 476 MIRBuilder.buildSExt(NewReg, ValReg); 477 return NewReg; 480 Register NewReg = MRI.createGenericVirtualRegister(LocTy); 481 MIRBuilder.buildZExt(NewReg, ValReg); 482 return NewReg; [all...] |
H A D | RegisterBankInfo.cpp | 469 Register NewReg = *NewRegs.begin(); local 471 MO.setReg(NewReg); 472 LLVM_DEBUG(dbgs() << " with " << printReg(NewReg, nullptr)); 477 LLT NewTy = MRI.getType(NewReg); 488 MRI.setType(NewReg, OrigTy);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
H A D | DbgEntityHistoryCalculator.cpp | 186 if (Register NewReg = isDescribedByReg(DV)) { 187 if (!TrackedRegs.count(NewReg)) 188 addRegDescribedVar(RegVars, NewReg, Var); 190 TrackedRegs[NewReg] = true;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FlagsCopyLowering.cpp | 996 unsigned NewReg; 1010 NewReg = MRI->createVirtualRegister(&X86::GR32RegClass); 1011 BuildMI(MBB, SetPos, SetLoc, TII->get(X86::MOVZX32rr8), NewReg) 1014 return NewReg; 1015 Reg = NewReg; 1019 NewReg = MRI->createVirtualRegister(&SetBRC); 1022 NewReg) 1033 NewReg) 1036 BuildMI(MBB, SetPos, SetLoc, TII->get(TargetOpcode::COPY), NewReg) 1039 return NewReg; [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 630 unsigned NewReg = optimizeSDPattern(MI); local 632 if (NewReg != 0) { 638 // reference into a plain DPR, and that will end poorly. NewReg is 641 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg())); 644 << printReg(NewReg) << "\n"); 645 (*I)->substVirtReg(NewReg, 0, *TRI); 648 Replacements[MI] = NewReg;
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H A D | ARMBaseRegisterInfo.h | 159 void updateRegAllocHint(unsigned Reg, unsigned NewReg,
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H A D | ARMBaseRegisterInfo.cpp | 355 ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg, argument 370 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 371 if (Register::isVirtualRegister(NewReg)) 372 MRI->setRegAllocationHint(NewReg,
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TailDuplicator.h | 98 void addSSAUpdateEntry(unsigned OrigReg, unsigned NewReg,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | RDFCopy.cpp | 179 unsigned NewReg = MinPhysReg(SR); local 180 Op.setReg(NewReg);
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