/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonCFGOptimizer.cpp | 84 int NewOpcode = 0; local 87 NewOpcode = Hexagon::J2_jumpf; 90 NewOpcode = Hexagon::J2_jumpt; 93 NewOpcode = Hexagon::J2_jumpfnewpt; 96 NewOpcode = Hexagon::J2_jumptnewpt; 102 MI.setDesc(TII->get(NewOpcode));
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H A D | HexagonVLIWPacketizer.cpp | 455 int NewOpcode; local 457 NewOpcode = HII->getDotNewPredOp(MI, MBPI); 459 NewOpcode = HII->getDotNewOp(MI); 460 MI.setDesc(HII->get(NewOpcode)); 465 int NewOpcode = HII->getDotOldOp(MI); local 466 MI.setDesc(HII->get(NewOpcode)); 884 int NewOpcode = HII->getDotNewOp(MI); local 885 const MCInstrDesc &D = HII->get(NewOpcode);
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H A D | HexagonInstrInfo.cpp | 1534 unsigned NewOpcode = getInvertedPredicatedOpcode(opcode); local 1535 Cond[0].setImm(NewOpcode); 3667 int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode()); 3668 if (NewOpcode >= 0) 3669 return NewOpcode; 4372 unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode()); local 4381 NewOpcode = reversePrediction(NewOpcode); 4383 MI.setDesc(get(NewOpcode));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | MVEVPTBlockPass.cpp | 76 unsigned &NewOpcode) { 83 if (!(NewOpcode = VCMPOpcodeToVPT(Def->getOpcode()))) 144 unsigned NewOpcode; local 145 MachineInstr *VCMP = findVCMPToFoldIntoVPST(MI, RDA, NewOpcode); 148 MIBuilder = BuildMI(Block, MI, dl, TII->get(NewOpcode)); 74 findVCMPToFoldIntoVPST(MachineInstr *MI, ReachingDefAnalysis *RDA, unsigned &NewOpcode) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.cpp | 137 int NewOpcode; local 139 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; 140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) 145 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; 146 BuildMI(MBB, II, dl, TII.get(NewOpcode)) 152 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; 153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCOptAddrMode.cpp | 100 void changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode, 253 int NewOpcode = ARC::getPostIncOpcode(Ldst.getOpcode()); local 254 assert(NewOpcode > 0 && "No postincrement form found"); 256 changeToAddrMode(Ldst, NewOpcode, NewBaseReg, Add.getOperand(2)); 441 void ARCOptAddrMode::changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode, argument 459 Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FixupLEAs.cpp | 389 unsigned NewOpcode = getADDrrFromLEA(MI.getOpcode()); local 395 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) 400 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) 412 unsigned NewOpcode = getINCDECFromLEA(MI.getOpcode(), IsINC); local 416 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) 419 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) 423 unsigned NewOpcode = getADDriFromLEA(MI.getOpcode(), Disp); local 426 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) 430 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
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H A D | X86InstrInfo.cpp | 3575 unsigned NewOpcode = 0; local 3578 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; 3579 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; 3580 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; 3581 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; 3582 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; 3583 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; 3584 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; 3585 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; 3586 case X86::SUB64ri32: NewOpcode [all...] |
H A D | X86MCInstLower.cpp | 316 unsigned NewOpcode = 0; local 323 NewOpcode = X86::CBW; 327 NewOpcode = X86::CWDE; 331 NewOpcode = X86::CDQE; 335 if (NewOpcode != 0) { 337 Inst.setOpcode(NewOpcode);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDILCFGStructurizer.cpp | 222 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode, 224 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode, 226 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode); 227 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode, 230 MachineBasicBlock::iterator I, int NewOpcode, 457 int NewOpcode, const DebugLoc &DL) { 459 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); 466 int NewOpcode, 469 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); 479 MachineBasicBlock::iterator I, int NewOpcode) { 456 insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode, const DebugLoc &DL) argument 465 insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode, const DebugLoc &DL) argument 478 insertInstrBefore( MachineBasicBlock::iterator I, int NewOpcode) argument 490 insertCondBranchBefore( MachineBasicBlock::iterator I, int NewOpcode, const DebugLoc &DL) argument 503 insertCondBranchBefore( MachineBasicBlock *blk, MachineBasicBlock::iterator I, int NewOpcode, int RegNum, const DebugLoc &DL) argument [all...] |
H A D | SIShrinkInstructions.cpp | 292 unsigned NewOpcode = local 295 MI.setDesc(TII->get(NewOpcode));
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H A D | SIInstrInfo.cpp | 4836 unsigned NewOpcode = getVALUOp(Inst); 4915 NewOpcode = AMDGPU::V_LSHLREV_B32_e64; 4921 NewOpcode = AMDGPU::V_ASHRREV_I32_e64; 4927 NewOpcode = AMDGPU::V_LSHRREV_B32_e64; 4933 NewOpcode = AMDGPU::V_LSHLREV_B64; 4939 NewOpcode = AMDGPU::V_ASHRREV_I64; 4945 NewOpcode = AMDGPU::V_LSHRREV_B64; 5007 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) { 5015 const MCInstrDesc &NewDesc = get(NewOpcode);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiRegisterInfo.cpp | 233 unsigned NewOpcode = getOppositeALULoOpcode(MI.getOpcode()); local 238 BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode),
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.cpp | 193 int NewOpcode = -1; local 196 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); 197 if (NewOpcode == -1) 198 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); 201 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); 204 if (NewOpcode == -1) 205 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); 207 if (NewOpcode != -1) { 211 TmpInst.setOpcode (NewOpcode);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZFrameLowering.cpp | 604 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); local 608 if (!NewOpcode) { 613 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); 614 assert(NewOpcode && "No restore instruction available"); 617 MBBI->setDesc(ZII->get(NewOpcode));
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H A D | SystemZInstrInfo.cpp | 64 // each having the opcode given by NewOpcode. 66 unsigned NewOpcode) const { 107 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); 108 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); 125 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); local 126 assert(NewOpcode && "No support for huge argument lists yet"); 127 MI->setDesc(get(NewOpcode)); 966 unsigned NewOpcode; local 968 NewOpcode = SystemZ::RISBG; 971 NewOpcode [all...] |
H A D | SystemZInstrInfo.h | 164 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | CombinerHelper.cpp | 743 unsigned NewOpcode; local 746 NewOpcode = TargetOpcode::G_INDEXED_LOAD; 749 NewOpcode = TargetOpcode::G_INDEXED_SEXTLOAD; 752 NewOpcode = TargetOpcode::G_INDEXED_ZEXTLOAD; 755 NewOpcode = TargetOpcode::G_INDEXED_STORE; 761 auto MIB = MIRBuilder.buildInstr(NewOpcode);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
H A D | AMDGPUDisassembler.cpp | 533 int NewOpcode = local 535 if (NewOpcode == -1) 541 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 564 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 571 MI.setOpcode(NewOpcode);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/AsmParser/ |
H A D | PPCAsmParser.cpp | 1561 std::string NewOpcode; local 1563 NewOpcode = Name; 1564 NewOpcode += '+'; 1565 Name = NewOpcode; 1568 NewOpcode = Name; 1569 NewOpcode += '-'; 1570 Name = NewOpcode; 1576 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1584 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 6344 unsigned NewOpcode; local 6348 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break; 6349 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break; 6350 case PPC::SLW: NewOpcode = PPC::SLW8; break; 6351 case PPC::SRW: NewOpcode = PPC::SRW8; break; 6352 case PPC::LI: NewOpcode = PPC::LI8; break; 6353 case PPC::LIS: NewOpcode = PPC::LIS8; break; 6354 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break; 6355 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break; 6356 case PPC::CNTLZW: NewOpcode [all...] |
H A D | PPCAsmPrinter.cpp | 1137 unsigned NewOpcode = local 1141 EmitToStreamer(*OutStreamer, MCInstBuilder(NewOpcode) 1151 unsigned NewOpcode = local 1157 EmitToStreamer(*OutStreamer, MCInstBuilder(NewOpcode)
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H A D | PPCRegisterInfo.cpp | 1152 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; variable 1153 MI.setDesc(TII.get(NewOpcode));
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | InstructionSelectorImpl.h | 753 int64_t NewOpcode = MatchTable[CurrentIdx++]; local 759 OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode)); 763 << NewOpcode << ")\n"); local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsDelaySlotFiller.cpp | 566 unsigned NewOpcode = TII->getEquivalentCompactForm(Branch); local 567 Branch = TII->genInstrWithNewOpc(NewOpcode, Branch);
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