Searched refs:MUL (Results 1 - 25 of 64) sorted by relevance

123

/freebsd-11-stable/lib/libc/quad/TESTS/
H A DMakefile5 MUL= mul.c ../muldi3.c macro
6 mul: ${MUL}
7 gcc -g -DSPARC_XXX ${MUL} -o ${.TARGET}
/freebsd-11-stable/contrib/byacc/test/btyacc/
H A Dquote_calc.tab.h9 #define MUL 262 macro
H A Dquote_calc2.tab.h9 #define MUL 262 macro
/freebsd-11-stable/contrib/byacc/test/yacc/
H A Dquote_calc.tab.h6 #define MUL 262 macro
H A Dquote_calc2.tab.h6 #define MUL 262 macro
H A Dquote_calc2.tab.c154 #define MUL 262 macro
272 0,0,0,0,0,0,"OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
286 "expr : expr \"MUL\" expr",
H A Dquote_calc.tab.c154 #define MUL 262 macro
272 0,0,0,0,0,0,"OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3582 // 32b Opcodes that can be combined with a MUL
3601 // 64b Opcodes that can be combined with a MUL
3660 // Opcodes that can be combined with a MUL
4151 /// F|MUL I=A,B,0
4161 /// the F|MUL. In the example above IdxMulOpd is 1.
4177 MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg()); local
4179 Register SrcReg0 = MUL->getOperand(1).getReg();
4180 bool Src0IsKill = MUL->getOperand(1).isKill();
4181 Register SrcReg1 = MUL->getOperand(2).getReg();
4182 bool Src1IsKill = MUL
4328 MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg()); local
4367 MachineInstr *MUL; local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiTargetTransformInfo.h92 case ISD::MUL:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXTargetTransformInfo.cpp129 case ISD::MUL:
/freebsd-11-stable/contrib/byacc/test/
H A Dbtyacc_demo.y22 enum Operator { ADD, SUB, MUL, MOD, DIV, DEREF };
174 | expr '*' expr($e) { $$ = build_expr($1, MUL, $3); }
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp198 { ISD::MUL, MVT::v4i32, 11 }, // pmulld
199 { ISD::MUL, MVT::v8i16, 2 }, // pmullw
200 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence.
215 { ISD::MUL, MVT::v2i64, 17 },
222 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) {
487 { ISD::MUL, MVT::v2i64, 1 },
488 { ISD::MUL, MVT::v4i64, 1 },
489 { ISD::MUL, MVT::v8i64, 1 }
514 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence.
515 { ISD::MUL, MV
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp582 if (Shl_0.getOpcode() == ISD::MUL) {
1614 case ISD::MUL:
1703 if (Opcode == ISD::MUL &&
1770 if (Val.getOpcode() != ISD::MUL ||
1798 if (Val.getOpcode() == ISD::MUL) {
1821 if (V.getOpcode() == ISD::MUL) {
1838 if (V.getOpcode() == ISD::MUL) {
1940 // SHL nodes will be converted to MUL nodes
1942 NOpcode = ISD::MUL;
1989 (Child.getOpcode() == ISD::MUL || Chil
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H A DHexagonISelLoweringHVX.cpp91 setOperationAction(ISD::MUL, T, Custom);
150 setOperationAction(ISD::MUL, T, Custom);
699 IdxV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, ScV);
760 IdxV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, ScV);
927 IdxV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
987 ByteIdx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
1305 // For i16 there is V6_vmpyih, which acts exactly like the MUL opcode.
1542 case ISD::MUL:
1577 case ISD::MUL: return LowerHvxMul(Op, DAG);
H A DHexagonISelLowering.cpp1474 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
1546 setOperationAction(ISD::MUL, NativeVT, Legal);
2356 SDValue I0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, M0);
2370 SDValue S0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2412 SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2448 SDValue Idx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2482 SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, WidthV);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h202 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGAddressAnalysis.cpp236 // MUL instruction. In this case Base is the actual BASE pointer.
240 if (Base->getOperand(1)->getOpcode() == ISD::MUL)
H A DTargetLowering.cpp1985 case ISD::MUL:
2541 // TODO: There are more binop opcodes that could be handled here - MUL, MIN,
2583 case ISD::MUL:
4691 return DAG.getNode(ISD::MUL, dl, VT, Res, Factor);
4780 // FIXME: We should support doing a MUL in a wider type.
4795 Factor = DAG.getNode(ISD::MUL, dl, VT, N0, Factor);
4900 // FIXME: We should support doing a MUL in a wider type.
5015 // If MUL is unavailable, we cannot proceed in any case.
5016 if (!isOperationLegalOrCustom(ISD::MUL, VT))
5154 SDValue Op0 = DAG.getNode(ISD::MUL, D
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H A DSelectionDAGBuilder.h698 void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
H A DLegalizeIntegerTypes.cpp133 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
1836 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
2967 SDValue T = DAG.getNode(ISD::MUL, dl, NVT, LLL, RLL);
2982 DAG.getNode(ISD::MUL, dl, NVT, LLH, RLL), TH);
2987 DAG.getNode(ISD::MUL, dl, NVT, LLL, RLH), UL);
2991 DAG.getNode(ISD::MUL, dl, NVT, LLH, RLH),
2998 DAG.getNode(ISD::MUL, dl, NVT, RH, LL),
2999 DAG.getNode(ISD::MUL, dl, NVT, RL, LH)));
3049 Result = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3573 SDValue Three = DAG.getNode(ISD::MUL, d
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H A DLegalizeDAG.cpp3290 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3330 Results.push_back(DAG.getNode(ISD::MUL, dl, VT, LHS, RHS));
3354 case ISD::MUL: {
3554 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
4177 case ISD::MUL:
4322 case ISD::MUL:
4367 Tmp1 = DAG.getNode(ISD::MUL, dl, NVT, Tmp1, Tmp2);
4592 SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4640 SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
H A DFastISel.cpp754 IdxN = fastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT);
1824 return selectBinaryOp(I, ISD::MUL);
1994 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp599 if (OtherOp.getOpcode() == ISD::MUL) {
609 if (AddOp.getOperand(0).getOpcode() == ISD::MUL) {
619 if (AddOp.getOperand(1).getOpcode() == ISD::MUL) {
637 if (N->getOperand(0).getOpcode() == ISD::MUL) {
640 } else if (N->getOperand(1).getOpcode() == ISD::MUL) {
685 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH);
686 LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp115 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
189 setOperationAction(ISD::MUL, MVT::i64, Legal);
191 setOperationAction(ISD::MUL, MVT::i64, Custom);
211 setTargetDAGCombine(ISD::MUL);
232 setOperationAction(ISD::MUL, MVT::i32, Legal);
279 setOperationAction(ISD::MUL, MVT::i64, Legal);
337 setOperationAction(ISD::MUL, Ty, Legal);
458 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
1037 case ISD::MUL:
2003 DAG.getNode(ISD::MUL, SDLo
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp337 setOperationAction(ISD::MUL, MVT::i64, Expand);
366 setOperationAction(ISD::MUL, VT, Expand);
491 setTargetDAGCombine(ISD::MUL);
1617 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1705 SDValue Mullo1 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Rcp64);
1720 SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1);
1737 SDValue Mul3 = DAG.getNode(ISD::MUL, DL, VT, RHS, Mulhi3);
1872 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1903 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
3991 case ISD::MUL
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