Searched refs:IsAdd (Results 1 - 15 of 15) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp454 unsigned Reg, int NumBytes, bool IsAdd,
458 Opc = IsAdd ? ARC::ADD_rru6 : ARC::SUB_rru6;
460 Opc = IsAdd ? ARC::ADD_rrs12 : ARC::SUB_rrs12;
462 Opc = IsAdd ? ARC::ADD_rrlimm : ARC::SUB_rrlimm;
486 bool IsAdd = (Old.getOpcode() == ARC::ADJCALLSTACKUP); local
487 emitRegUpdate(MBB, I, dl, ARC::SP, Amt, IsAdd, TII);
452 emitRegUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned Reg, int NumBytes, bool IsAdd, const ARCInstrInfo *TII) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp397 const bool IsAdd = I.getOpcode() == AMDGPU::G_UADDO || local
406 unsigned NoCarryOpc = IsAdd ? AMDGPU::V_ADD_I32_e64 : AMDGPU::V_SUB_I32_e64;
407 unsigned CarryOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64;
422 unsigned NoCarryOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
423 unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
H A DAMDGPUISelDAGToDAG.cpp1006 bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE; local
1023 unsigned Opc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
1024 unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
H A DSIInstrInfo.cpp5352 bool IsAdd = (Inst.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO);
5387 unsigned LoOpc = IsAdd ? AMDGPU::V_ADD_I32_e64 : AMDGPU::V_SUB_I32_e64;
5395 unsigned HiOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64;
H A DSIISelLowering.cpp3633 bool IsAdd = (MI.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO); local
3635 unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
3636 unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp7401 bool IsAdd = Node->getOpcode() == ISD::UADDO;
7404 unsigned OpcCarry = IsAdd ? ISD::ADDCARRY : ISD::SUBCARRY;
7414 Result = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl,
7420 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
7430 bool IsAdd = Node->getOpcode() == ISD::SADDO;
7432 Result = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl,
7440 unsigned OpcSat = IsAdd ? ISD::SADDSAT : ISD::SSUBSAT;
7458 DAG.getSetCC(dl, OType, RHS, Zero, IsAdd ? ISD::SETLT : ISD::SETGT);
H A DLegalizeDAG.cpp3446 bool IsAdd = Node->getOpcode() == ISD::ADDCARRY;
3449 unsigned Op = IsAdd ? ISD::ADD : ISD::SUB;
3456 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
3470 IsAdd ? DAG.getSetCC(dl, SetCCType, Sum2, Zero, ISD::SETEQ)
H A DDAGCombiner.cpp2016 bool IsAdd = N->getOpcode() == ISD::ADD; local
2017 SDValue C = IsAdd ? N->getOperand(1) : N->getOperand(0);
2018 SDValue Z = IsAdd ? N->getOperand(0) : N->getOperand(1);
2043 SDValue C1 = IsAdd ? DAG.getConstant(CN->getAPIntValue() + 1, DL, VT) :
2045 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, C1, LowBit);
2057 bool IsAdd = N->getOpcode() == ISD::ADD; local
2058 SDValue ConstantOp = IsAdd ? N->getOperand(1) : N->getOperand(0);
2059 SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1);
2080 auto ShOpcode = IsAdd ? ISD::SRA : ISD::SRL;
2082 APInt NewC = IsAdd
2418 foldAddSubMasked1(bool IsAdd, SDValue N0, SDValue N1, SelectionDAG &DAG, const SDLoc &DL) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/IR/
H A DAutoUpgrade.cpp2375 bool IsAdd = Name.contains(".padds"); local
2376 Rep = UpgradeX86AddSubSatIntrinsics(Builder, *CI, true, IsAdd);
2383 bool IsAdd = Name.contains(".paddus"); local
2384 Rep = UpgradeX86AddSubSatIntrinsics(Builder, *CI, false, IsAdd);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DValueTracking.cpp1626 bool IsAdd = II->getIntrinsicID() == Intrinsic::uadd_sat; local
1634 if (IsAdd)
1642 IsAdd, /* NSW */ false, Known, Known2);
1646 if (IsAdd) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineSelect.cpp1768 auto IsSignedSaturateLimit = [&](Value *Limit, bool IsAdd) {
1791 if (IsAdd) {
1842 IsSignedSaturateLimit(TrueVal, /*IsAdd=*/true))
1853 IsSignedSaturateLimit(TrueVal, /*IsAdd=*/false))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp4365 const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO;
4370 if (IsAdd)
4388 IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero);
/freebsd-11-stable/contrib/llvm-project/clang/lib/Sema/
H A DSemaOpenMP.cpp6200 bool IsAdd = BO->getOpcode() == BO_Add;
6202 return setStep(BO->getRHS(), !IsAdd);
6203 if (IsAdd && getInitLCDecl(BO->getRHS()) == LCDecl)
6207 bool IsAdd = CE->getOperator() == OO_Plus;
6208 if ((IsAdd || CE->getOperator() == OO_Minus) && CE->getNumArgs() == 2) {
6210 return setStep(CE->getArg(1), !IsAdd);
6211 if (IsAdd && getInitLCDecl(CE->getArg(1)) == LCDecl)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1040 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD; local
1041 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4559 bool IsAdd = Op->getOpcode() == ISD::SADDSAT; local
4564 NewOpcode = IsAdd ? ARMISD::QADD8b : ARMISD::QSUB8b;
4567 NewOpcode = IsAdd ? ARMISD::QADD16b : ARMISD::QSUB16b;

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