| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | StructurizeCFG.cpp | 221 Value *buildCondition(BranchInst *Term, unsigned Idx, bool Invert);
404 /// Invert the given condition
439 bool Invert) {
440 Value *Cond = Invert ? BoolFalse : BoolTrue;
444 if (Idx != (unsigned)Invert)
438 buildCondition(BranchInst *Term, unsigned Idx, bool Invert) argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 653 bool Invert) const;
661 bool Invert = false) const;
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| H A D | SystemZISelLowering.cpp | 2706 // or 0 if neither can be done directly. Indicate in Invert whether the
2709 bool &Invert) {
2711 Invert = false;
2717 Invert = true;
2792 bool Invert = false;
2797 Invert = true;
2814 Invert = true;
2833 if (unsigned Opcode = getVectorComparisonOrInvert(CC, Mode, Invert))
2837 if (unsigned Opcode = getVectorComparisonOrInvert(CC, Mode, Invert))
2846 if (Invert) {
6190 bool Invert = false; local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 499 bool Invert = !DefMI; local
506 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2);
523 if (Invert)
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| H A D | LanaiISelLowering.cpp | 1341 // * Invert is set when N is the all zero/ones constant when CC is false.
1345 // * X = 0, Invert = False and OtherOp = Y
1346 // * Y = 0, Invert = True and OtherOp = X
1348 bool &Invert, SDValue &OtherOp,
1358 Invert = false;
1363 Invert = true;
1379 Invert = true;
1388 Invert = !AllOnes;
1347 isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG) argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 1171 bool Invert = false; local
1183 Invert = true;
1191 Invert = true;
1209 if (Invert)
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1644 bool &Invert) {
1645 Invert = false;
1652 Invert = true;
1665 Invert = true;
10898 bool Invert,
10954 if (Invert) {
12082 static SDValue getTestBitOperand(SDValue Op, unsigned &Bit, bool &Invert, argument
12096 return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
12102 return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
12119 return getTestBitOperand(Op->getOperand(0), Bit, Invert, DA
1641 changeVectorFPCCToAArch64CC(ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2, bool &Invert) argument
10897 tryConvertSVEWideCompare(SDNode *N, unsigned ReplacementIID, bool Invert, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
12159 bool Invert = false; local
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | SimplifyCFG.cpp | 1974 bool Invert = false; local
1977 Invert = true;
1979 assert(EndBB == BI->getSuccessor(!Invert) && "No edge from to end block");
2102 if (Invert)
2136 if (Invert)
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 3893 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) { argument
3894 Invert = false;
3905 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
3907 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
3909 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
3910 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 2238 bool Invert = !DefMI; local
2245 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1);
2263 if (Invert)
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| H A D | ARMISelLowering.cpp | 3843 // Invert the bits.
6215 bool Invert = false; local
6275 Invert = true; LLVM_FALLTHROUGH;
6288 case ISD::SETULE: Invert = true; Opc = ARMCC::GT; break;
6290 case ISD::SETULT: Invert = true; Opc = ARMCC::GE; break;
6291 case ISD::SETUEQ: Invert = true; LLVM_FALLTHROUGH;
6299 if (Invert)
6303 case ISD::SETUO: Invert = true; LLVM_FALLTHROUGH;
6311 if (Invert)
6324 Invert
10980 isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG) argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 21609 bool Invert = false;
21613 case ISD::SETUGT: Invert = true; LLVM_FALLTHROUGH;
21615 case ISD::SETULT: Invert = true; LLVM_FALLTHROUGH;
21623 if (Invert)
21640 bool Invert = Cond == ISD::SETNE ||
21654 if (!FlipSigns && !Invert && ISD::isBuildVectorAllZeros(Op0.getNode())) {
21665 if (!FlipSigns && !Invert && ISD::isBuildVectorAllOnes(Op1.getNode())) {
21706 if (Invert)
21729 if (Invert)
21749 if (Invert)
[all...] |
| /freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 193 bool Invert = false) {
217 if (Invert)
14325 // Invert the mask to only clear the lower bits.
|