/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
H A D | MCInstBuilder.h | 22 MCInst Inst; member in class:llvm::MCInstBuilder 27 Inst.setOpcode(Opcode); 32 Inst.addOperand(MCOperand::createReg(Reg)); 38 Inst.addOperand(MCOperand::createImm(Val)); 44 Inst.addOperand(MCOperand::createFPImm(Val)); 50 Inst.addOperand(MCOperand::createExpr(Val)); 56 Inst.addOperand(MCOperand::createInst(Val)); 62 Inst.addOperand(Op); 67 return Inst;
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H A D | MCInstrAnalysis.h | 37 virtual bool isBranch(const MCInst &Inst) const { 38 return Info->get(Inst.getOpcode()).isBranch(); 41 virtual bool isConditionalBranch(const MCInst &Inst) const { 42 return Info->get(Inst.getOpcode()).isConditionalBranch(); 45 virtual bool isUnconditionalBranch(const MCInst &Inst) const { 46 return Info->get(Inst.getOpcode()).isUnconditionalBranch(); 49 virtual bool isIndirectBranch(const MCInst &Inst) const { 50 return Info->get(Inst.getOpcode()).isIndirectBranch(); 53 virtual bool isCall(const MCInst &Inst) const { 54 return Info->get(Inst [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 75 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, 80 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, 85 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, 88 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val, 91 static DecodeStatus Decode2RInstruction(MCInst &Inst, 96 static DecodeStatus Decode2RImmInstruction(MCInst &Inst, 101 static DecodeStatus DecodeR2RInstruction(MCInst &Inst, 106 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, 111 static DecodeStatus DecodeRUSInstruction(MCInst &Inst, 116 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, 198 DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 210 DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 222 DecodeBitpOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 233 DecodeNegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 274 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 344 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 357 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 370 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 383 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 397 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 410 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 423 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 437 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 508 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 522 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 536 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 549 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 562 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 575 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 588 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 602 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 617 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 631 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 645 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 665 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 679 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 699 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 718 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/ |
H A D | MCInstrAnalysis.cpp | 20 const MCInst &Inst, 26 bool MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr, argument 28 if (Inst.getNumOperands() == 0 || 29 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL) 32 int64_t Imm = Inst.getOperand(0).getImm(); 38 MCInstrAnalysis::evaluateMemoryOperandAddress(const MCInst &Inst, uint64_t Addr, argument 19 clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, APInt &Writes) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/Disassembler/ |
H A D | SystemZDisassembler.cpp | 82 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, argument 88 Inst.addOperand(MCOperand::createReg(RegNo)); 92 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, 95 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16); 98 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo, 101 return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16); 104 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, 107 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16); 110 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, 113 return decodeRegisterClass(Inst, RegN [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/ |
H A D | PPCDisassembler.cpp | 63 static DecodeStatus DecodePCRel24BranchTarget(MCInst &Inst, unsigned Imm, argument 67 Inst.addOperand(MCOperand::createImm(Offset)); 75 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, argument 78 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); 82 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 85 return decodeRegisterClass(Inst, RegNo, CRRegs); 88 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, 91 return decodeRegisterClass(Inst, RegNo, CRBITRegs); 94 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, 97 return decodeRegisterClass(Inst, RegN [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/ |
H A D | RISCVDisassembler.cpp | 59 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, argument 72 Inst.addOperand(MCOperand::createReg(Reg)); 76 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, argument 83 Inst.addOperand(MCOperand::createReg(Reg)); 87 static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo, argument 94 Inst.addOperand(MCOperand::createReg(Reg)); 98 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, argument 105 Inst.addOperand(MCOperand::createReg(Reg)); 109 static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo, argument 116 Inst 120 DecodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) argument 130 DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) argument 140 DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) argument 153 addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) argument 170 decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument 179 decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument 188 decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument 198 decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument 207 decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument 218 decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument 229 decodeFRMArg(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) argument 259 decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 269 decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 281 decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 294 decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 303 decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Utils/ |
H A D | RISCVMatInt.h | 20 struct Inst { struct in namespace:llvm::RISCVMatInt 24 Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {} function in struct:llvm::RISCVMatInt::Inst 26 using InstSeq = SmallVector<Inst, 8>;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | Sink.cpp | 37 static bool AllUsesDominatedByBlock(Instruction *Inst, BasicBlock *BB, argument 43 for (Use &U : Inst->uses()) { 60 static bool isSafeToMove(Instruction *Inst, AliasAnalysis &AA, argument 63 if (Inst->mayWriteToMemory()) { 64 Stores.insert(Inst); 68 if (LoadInst *L = dyn_cast<LoadInst>(Inst)) { 75 if (Inst->isTerminator() || isa<PHINode>(Inst) || Inst->isEHPad() || 76 Inst 95 IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo, DominatorTree &DT, LoopInfo &LI) argument 139 SinkInstruction(Instruction *Inst, SmallPtrSetImpl<Instruction *> &Stores, DominatorTree &DT, LoopInfo &LI, AAResults &AA) argument 217 Instruction *Inst = &*I; // The instruction to sink. local [all...] |
H A D | EarlyCSE.cpp | 97 Instruction *Inst; member in struct:__anon2667::SimpleValue 99 SimpleValue(Instruction *I) : Inst(I) { 100 assert((isSentinel() || canHandle(I)) && "Inst can't be handled!"); 104 return Inst == DenseMapInfo<Instruction *>::getEmptyKey() || 105 Inst == DenseMapInfo<Instruction *>::getTombstoneKey(); 108 static bool canHandle(Instruction *Inst) { argument 110 if (CallInst *CI = dyn_cast<CallInst>(Inst)) 112 return isa<CastInst>(Inst) || isa<UnaryOperator>(Inst) || 113 isa<BinaryOperator>(Inst) || is 204 Instruction *Inst = Val.Inst; local 410 Instruction *Inst; member in struct:__anon2668::CallValue 421 canHandle(Instruction *Inst) argument 453 Instruction *Inst = Val.Inst; local 526 LoadValue(Instruction *Inst, unsigned Generation, unsigned MatchingId, bool IsAtomic) argument 642 ParseMemoryInst(Instruction *Inst, const TargetTransformInfo &TTI) argument 731 Instruction *Inst; member in class:__anon2669::EarlyCSE::ParseMemoryInst 739 getOrCreateResult(Value *Inst, Type *ExpectedType) const argument 756 removeMSSA(Instruction *Inst) argument 938 Instruction *Inst = &*I++; local 1261 << " due to: " << *Inst << '\\n'); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 82 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 87 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 92 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 97 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 102 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 107 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 112 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 117 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 122 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 127 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 411 DecodeUImmWithOffset(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument 1395 DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1402 DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1414 DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1425 DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1436 DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1447 DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1458 DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1468 DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1475 DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1487 DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1499 DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1510 DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1521 DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1532 DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1554 DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1575 DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1593 DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1610 DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1627 DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1644 DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1661 DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1676 DecodeSyncI_MM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1689 DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1704 DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1750 DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1808 DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1824 DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1840 DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1865 DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1886 DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1921 DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1939 DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1957 DecodeFMemMMR2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1975 DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1993 DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2011 DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2029 DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2045 DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2067 DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 2078 DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 2090 DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 2102 DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 2114 DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 2126 DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 2138 DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 2150 DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 2162 DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 2174 DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 2186 DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 2198 DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 2210 DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 2219 DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 2228 DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2237 DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 2247 DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 2257 DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 2267 DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 2276 DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 2285 DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 2294 DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 2304 DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2313 DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2322 DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument 2335 DecodeLi16Imm(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument 2346 DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument 2355 DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument 2365 DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument 2373 DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2386 DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2392 DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2398 DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2412 DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2451 DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2475 DecodeMovePOperands(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2501 DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, uint64_t Address, const void *Decoder) argument 2543 DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, 62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 65 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 68 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigne 314 DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 325 DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 343 DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 364 DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 385 DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 406 DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 427 DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 438 DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 449 DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 471 DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 482 DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 505 DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void* Decoder) argument 516 DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 524 DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 543 DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void* Decoder) argument 567 DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void* Decoder) argument 591 DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void* Decoder) argument 608 DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 618 DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void* Decoder) argument 638 DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 660 DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 683 DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 706 DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 727 DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 750 DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 773 DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 783 DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 792 DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 799 DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 815 DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) argument 822 DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) argument 832 DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) argument 840 DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 863 DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add) argument 869 DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add) argument 875 DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 880 DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 886 DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 891 DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 897 DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 902 DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 908 DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 913 DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 918 DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 923 DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 928 DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 933 DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument 995 DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument 1028 DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument 1089 DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument 1287 DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument 1370 DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument 1504 DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument 1561 DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument 1592 DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument 1631 DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument 1649 DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument 1668 DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument 1704 DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument 1721 DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument 1751 DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument 1775 DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 1789 DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 1798 DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument 1807 DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument 1825 DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder) argument 1840 DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument 1852 DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | InstrInfoEmitter.cpp | 74 void emitRecord(const CodeGenInstruction &Inst, unsigned Num, 92 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst); 110 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { argument 113 for (auto &Op : Inst.Operands) { 207 for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) { 208 std::vector<std::string> OperandInfo = GetOperandInfo(*Inst); 233 for (const CodeGenInstruction *Inst : NumberedInstructions) { 234 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable")) 237 for (const auto &Info : Inst->Operands) { 247 Inst 536 Record *Inst = II->TheDef; local 650 emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map<std::vector<Record*>, unsigned> &EmittedLists, const OperandInfoMapTy &OpInfo, raw_ostream &OS) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | CFLGraph.h | 263 void visitReturnInst(ReturnInst &Inst) { 264 if (auto RetVal = Inst.getReturnValue()) { 272 void visitPtrToIntInst(PtrToIntInst &Inst) { 273 auto *Ptr = Inst.getOperand(0); 277 void visitIntToPtrInst(IntToPtrInst &Inst) { 278 auto *Ptr = &Inst; 282 void visitCastInst(CastInst &Inst) { 283 auto *Src = Inst.getOperand(0); 284 addAssignEdge(Src, &Inst); 287 void visitBinaryOperator(BinaryOperator &Inst) { [all...] |
H A D | PHITransAddr.cpp | 25 static bool CanPHITrans(Instruction *Inst) { argument 26 if (isa<PHINode>(Inst) || 27 isa<GetElementPtrInst>(Inst)) 30 if (isa<CastInst>(Inst) && 31 isSafeToSpeculativelyExecute(Inst)) 34 if (Inst->getOpcode() == Instruction::Add && 35 isa<ConstantInt>(Inst->getOperand(1))) 117 Instruction *Inst = dyn_cast<Instruction>(Addr); local 118 return !Inst || CanPHITrans(Inst); 147 Instruction *Inst = dyn_cast<Instruction>(V); local [all...] |
H A D | OrderedBasicBlock.cpp | 36 const Instruction *Inst = nullptr; local 50 Inst = cast<Instruction>(II); 51 NumberedInsts[Inst] = NextInstPos++; 52 if (Inst == A || Inst == B) 57 assert((Inst == A || Inst == B) && "Should find A or B"); 59 return Inst != B;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
H A D | VPlanTransforms.cpp | 50 Instruction *Inst = cast<Instruction>(VPInst->getUnderlyingValue()); local 51 if (DeadInstructions.count(Inst)) { 58 if (isa<LoadInst>(Inst) || isa<StoreInst>(Inst)) 60 *Inst, Plan->getOrAddVPValue(getLoadStorePointerOperand(Inst)), 62 else if (PHINode *Phi = dyn_cast<PHINode>(Inst)) { 69 } else if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Inst)) { 72 // If the last recipe is a VPWidenRecipe, add Inst to it instead of 76 WidenRecipe->appendInstruction(Inst); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
H A D | LanaiMCCodeEmitter.cpp | 51 uint64_t getBinaryCodeForInstr(const MCInst &Inst, 57 unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp, 61 unsigned getRiMemoryOpValue(const MCInst &Inst, unsigned OpNo, 65 unsigned getRrMemoryOpValue(const MCInst &Inst, unsigned OpNo, 69 unsigned getSplsOpValue(const MCInst &Inst, unsigned OpNo, 73 unsigned getBranchTargetOpValue(const MCInst &Inst, unsigned OpNo, 77 void encodeInstruction(const MCInst &Inst, raw_ostream &Ostream, 81 unsigned adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value, 84 unsigned adjustPqBitsSpls(const MCInst &Inst, unsigned Value, 110 const MCInst &Inst, cons 109 getMachineOpValue( const MCInst &Inst, const MCOperand &MCOp, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const argument 135 adjustPqBits(const MCInst &Inst, unsigned Value, unsigned PBitShift, unsigned QBitShift) argument 161 adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value, const MCSubtargetInfo &STI) const argument 167 adjustPqBitsSpls(const MCInst &Inst, unsigned Value, const MCSubtargetInfo &STI) const argument 172 encodeInstruction( const MCInst &Inst, raw_ostream &Ostream, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const argument 185 getRiMemoryOpValue( const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const argument 217 getRrMemoryOpValue( const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const argument 256 getSplsOpValue(const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const argument 288 getBranchTargetOpValue( const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/ObjCARC/ |
H A D | DependencyAnalysis.h | 61 Depends(DependenceKind Flavor, Instruction *Inst, const Value *Arg, 66 bool CanUse(const Instruction *Inst, const Value *Ptr, ProvenanceAnalysis &PA, 71 bool CanAlterRefCount(const Instruction *Inst, const Value *Ptr, 74 /// Returns true if we can not conservatively prove that Inst can not decrement 76 bool CanDecrementRefCount(const Instruction *Inst, const Value *Ptr, 79 static inline bool CanDecrementRefCount(const Instruction *Inst, argument 82 return CanDecrementRefCount(Inst, Ptr, PA, GetARCInstKind(Inst));
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H A D | DependencyAnalysis.cpp | 34 bool llvm::objcarc::CanAlterRefCount(const Instruction *Inst, const Value *Ptr, argument 47 const auto *Call = cast<CallBase>(Inst); 54 const DataLayout &DL = Inst->getModule()->getDataLayout(); 67 bool llvm::objcarc::CanDecrementRefCount(const Instruction *Inst, argument 76 return CanAlterRefCount(Inst, Ptr, PA, Class); 81 bool llvm::objcarc::CanUse(const Instruction *Inst, const Value *Ptr, argument 88 const DataLayout &DL = Inst->getModule()->getDataLayout(); 92 if (const ICmpInst *ICI = dyn_cast<ICmpInst>(Inst)) { 98 } else if (auto CS = ImmutableCallSite(Inst)) { 108 } else if (const StoreInst *SI = dyn_cast<StoreInst>(Inst)) { 131 Depends(DependenceKind Flavor, Instruction *Inst, const Value *Arg, ProvenanceAnalysis &PA) argument 251 Instruction *Inst = &*--LocalStartPos; local [all...] |
H A D | ObjCARCExpand.cpp | 98 Instruction *Inst = &*I; local 100 LLVM_DEBUG(dbgs() << "ObjCARCExpand: Visiting: " << *Inst << "\n"); 102 switch (GetBasicARCInstKind(Inst)) { 114 Value *Value = cast<CallInst>(Inst)->getArgOperand(0); 115 LLVM_DEBUG(dbgs() << "ObjCARCExpand: Old = " << *Inst 119 Inst->replaceAllUsesWith(Value);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/MCA/ |
H A D | CodeEmitter.cpp | 25 const MCInst &Inst = Sequence[MCID]; local 27 if (MAB.mayNeedRelaxation(Inst, STI)) 28 MAB.relaxInstruction(Inst, STI, Relaxed);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 177 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 183 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 185 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 188 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 191 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 195 MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 198 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigne 1127 DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1137 DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1152 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1165 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1180 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1198 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1207 DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1219 DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1234 DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1245 DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1275 DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1300 DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1310 DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1326 DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1341 DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1348 DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1356 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1370 DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1390 DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1411 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1423 DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1440 DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1449 DecodeSORegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1486 DecodeSORegRegOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1521 DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1568 DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1592 DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1617 DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1644 DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1823 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1928 DecodeSORegMemOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1972 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2163 DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2192 DecodeQADDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2215 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2307 DecodeHINTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2329 DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2376 DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2418 DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2442 DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2469 DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2497 DecodeTSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2518 DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2546 DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2566 DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2586 DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2606 DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2612 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2639 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2664 DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2681 DecodeVLDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2957 DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2970 DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2985 DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2998 DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3008 DecodeVSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3278 DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3325 DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3373 DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3408 DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3461 DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3507 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3535 DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3560 DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3579 DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3585 DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3591 DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3597 DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3603 DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3639 DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3663 DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3671 DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3679 DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3687 DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3702 DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3716 DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3726 DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3734 DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3763 DecodeT2LoadShift(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3846 DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument 3930 DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument 4010 DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument 4049 DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument 4102 DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4116 DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4131 DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4146 DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4162 DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, uint64_t Address, const void *Decoder) argument 4177 DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4190 DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4204 DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4251 DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4268 DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4286 DecodeT2LdStPre(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4347 DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4373 DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 4384 DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 4409 DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 4420 DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4433 DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4448 DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4470 DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4494 DecodeCoprocessor(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4510 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4526 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4568 DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4600 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4608 DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4632 DecodeMemBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4641 DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4650 DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4732 DecodeBankedReg(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4747 DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4768 DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4794 DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4819 DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4846 DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4871 DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4896 DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4963 DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5028 DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5095 DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5158 DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5228 DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5291 DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5372 DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5444 DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5470 DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5496 DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5526 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5563 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5597 DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, const void *Decoder) argument 5623 DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, uint64_t Address, const void *Decoder) argument 5634 DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5661 DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5720 DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5779 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 5812 DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 5839 DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 5884 DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 5936 DecodeBFLabelOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 5955 DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 5967 DecodePredNoALOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 5976 DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 6038 DecodeLongShiftOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 6051 DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 6061 DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 6071 DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 6097 DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 6113 DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 6129 DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 6140 DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 6171 DecodeVpredROperand(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 6183 DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 6191 DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 6214 DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 6222 DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 6253 DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 6296 DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 6339 DecodeMVE_MEM_pre( MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder, unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) argument 6359 DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 6368 DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 6377 DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 6386 DecodePowerTwoOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 6399 DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 6409 DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 6419 DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 6442 DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 6467 DecodeMVEOverlappingLongShift( MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 6546 DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 6566 DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 6603 DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 6613 DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 6621 DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsAnalyzeImmediate.h | 19 struct Inst { struct in class:llvm::MipsAnalyzeImmediate 22 Inst(unsigned Opc, unsigned ImmOpnd); 24 using InstSeq = SmallVector<Inst, 7>; 35 void AddInstr(InstSeqLs &SeqLs, const Inst &I);
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/freebsd-11-stable/contrib/llvm-project/clang/include/clang/Sema/ |
H A D | TemplateInstCallback.h | 35 const Sema::CodeSynthesisContext &Inst) = 0; 39 const Sema::CodeSynthesisContext &Inst) = 0; 63 const Sema::CodeSynthesisContext &Inst) { 66 C->atTemplateBegin(TheSema, Inst); 73 const Sema::CodeSynthesisContext &Inst) { 76 C->atTemplateEnd(TheSema, Inst); 61 atTemplateBegin(TemplateInstantiationCallbackPtrs &Callbacks, const Sema &TheSema, const Sema::CodeSynthesisContext &Inst) argument 71 atTemplateEnd(TemplateInstantiationCallbackPtrs &Callbacks, const Sema &TheSema, const Sema::CodeSynthesisContext &Inst) argument
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