Lines Matching refs:Inst
82 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
87 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
92 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
97 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
102 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
107 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
112 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
117 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
122 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
127 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
132 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
137 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
142 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
146 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
151 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
156 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
161 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
166 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
171 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
176 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
181 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
186 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
191 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
196 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
201 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
206 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
211 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst,
216 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
221 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
226 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst,
231 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
238 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
245 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
252 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
259 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst,
266 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
273 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst,
278 static DecodeStatus DecodeMem(MCInst &Inst,
283 static DecodeStatus DecodeMemEVA(MCInst &Inst,
288 static DecodeStatus DecodeLoadByte15(MCInst &Inst,
293 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
296 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
301 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
306 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
311 static DecodeStatus DecodeSyncI(MCInst &Inst,
316 static DecodeStatus DecodeSyncI_MM(MCInst &Inst,
321 static DecodeStatus DecodeSynciR6(MCInst &Inst,
326 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
329 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
334 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
339 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
344 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
349 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
354 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
359 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
364 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
368 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
372 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
375 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
378 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
381 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
385 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
390 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
395 static DecodeStatus DecodeLi16Imm(MCInst &Inst,
400 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
406 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
411 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
414 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
419 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
423 static DecodeStatus DecodeInsSize(MCInst &Inst,
428 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
431 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
434 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
437 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
440 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
537 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
541 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
545 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
549 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
1395 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
1402 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
1410 Inst.addOperand(MCOperand::createReg(Reg));
1414 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
1421 Inst.addOperand(MCOperand::createReg(Reg));
1425 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
1432 Inst.addOperand(MCOperand::createReg(Reg));
1436 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
1443 Inst.addOperand(MCOperand::createReg(Reg));
1447 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
1454 Inst.addOperand(MCOperand::createReg(Reg));
1458 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1463 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1465 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1468 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1472 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1475 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1483 Inst.addOperand(MCOperand::createReg(Reg));
1487 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1495 Inst.addOperand(MCOperand::createReg(Reg));
1499 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1506 Inst.addOperand(MCOperand::createReg(Reg));
1510 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1517 Inst.addOperand(MCOperand::createReg(Reg));
1521 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1528 Inst.addOperand(MCOperand::createReg(Reg));
1532 static DecodeStatus DecodeMem(MCInst &Inst,
1543 if (Inst.getOpcode() == Mips::SC ||
1544 Inst.getOpcode() == Mips::SCD)
1545 Inst.addOperand(MCOperand::createReg(Reg));
1547 Inst.addOperand(MCOperand::createReg(Reg));
1548 Inst.addOperand(MCOperand::createReg(Base));
1549 Inst.addOperand(MCOperand::createImm(Offset));
1554 static DecodeStatus DecodeMemEVA(MCInst &Inst,
1565 if (Inst.getOpcode() == Mips::SCE)
1566 Inst.addOperand(MCOperand::createReg(Reg));
1568 Inst.addOperand(MCOperand::createReg(Reg));
1569 Inst.addOperand(MCOperand::createReg(Base));
1570 Inst.addOperand(MCOperand::createImm(Offset));
1575 static DecodeStatus DecodeLoadByte15(MCInst &Inst,
1586 Inst.addOperand(MCOperand::createReg(Reg));
1587 Inst.addOperand(MCOperand::createReg(Base));
1588 Inst.addOperand(MCOperand::createImm(Offset));
1593 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1603 Inst.addOperand(MCOperand::createReg(Base));
1604 Inst.addOperand(MCOperand::createImm(Offset));
1605 Inst.addOperand(MCOperand::createImm(Hint));
1610 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1620 Inst.addOperand(MCOperand::createReg(Base));
1621 Inst.addOperand(MCOperand::createImm(Offset));
1622 Inst.addOperand(MCOperand::createImm(Hint));
1627 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
1637 Inst.addOperand(MCOperand::createReg(Base));
1638 Inst.addOperand(MCOperand::createImm(Offset));
1639 Inst.addOperand(MCOperand::createImm(Hint));
1644 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
1654 Inst.addOperand(MCOperand::createReg(Base));
1655 Inst.addOperand(MCOperand::createImm(Offset));
1656 Inst.addOperand(MCOperand::createImm(Hint));
1661 static DecodeStatus DecodeSyncI(MCInst &Inst,
1670 Inst.addOperand(MCOperand::createReg(Base));
1671 Inst.addOperand(MCOperand::createImm(Offset));
1676 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
1683 Inst.addOperand(MCOperand::createReg(Base));
1684 Inst.addOperand(MCOperand::createImm(Offset));
1689 static DecodeStatus DecodeSynciR6(MCInst &Inst,
1698 Inst.addOperand(MCOperand::createReg(Base));
1699 Inst.addOperand(MCOperand::createImm(Immediate));
1704 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1713 Inst.addOperand(MCOperand::createReg(Reg));
1714 Inst.addOperand(MCOperand::createReg(Base));
1723 switch(Inst.getOpcode())
1731 Inst.addOperand(MCOperand::createImm(Offset));
1735 Inst.addOperand(MCOperand::createImm(Offset * 2));
1739 Inst.addOperand(MCOperand::createImm(Offset * 4));
1743 Inst.addOperand(MCOperand::createImm(Offset * 8));
1750 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1758 switch (Inst.getOpcode()) {
1762 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1772 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1778 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1782 switch (Inst.getOpcode()) {
1785 Inst.addOperand(MCOperand::createImm(-1));
1787 Inst.addOperand(MCOperand::createImm(Offset));
1791 Inst.addOperand(MCOperand::createImm(Offset));
1796 Inst.addOperand(MCOperand::createImm(Offset << 1));
1801 Inst.addOperand(MCOperand::createImm(Offset << 2));
1808 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1817 Inst.addOperand(MCOperand::createReg(Reg));
1818 Inst.addOperand(MCOperand::createReg(Mips::SP));
1819 Inst.addOperand(MCOperand::createImm(Offset << 2));
1824 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1833 Inst.addOperand(MCOperand::createReg(Reg));
1834 Inst.addOperand(MCOperand::createReg(Mips::GP));
1835 Inst.addOperand(MCOperand::createImm(Offset << 2));
1840 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
1845 switch (Inst.getOpcode()) {
1855 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1859 Inst.addOperand(MCOperand::createReg(Mips::SP));
1860 Inst.addOperand(MCOperand::createImm(Offset << 2));
1865 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
1876 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
1877 Inst.addOperand(MCOperand::createReg(Reg));
1879 Inst.addOperand(MCOperand::createReg(Reg));
1880 Inst.addOperand(MCOperand::createReg(Base));
1881 Inst.addOperand(MCOperand::createImm(Offset));
1886 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1897 switch (Inst.getOpcode()) {
1900 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1903 Inst.addOperand(MCOperand::createReg(Base));
1904 Inst.addOperand(MCOperand::createImm(Offset));
1907 Inst.addOperand(MCOperand::createReg(Reg));
1910 Inst.addOperand(MCOperand::createReg(Reg));
1911 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1912 Inst.addOperand(MCOperand::createReg(Reg+1));
1914 Inst.addOperand(MCOperand::createReg(Base));
1915 Inst.addOperand(MCOperand::createImm(Offset));
1921 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1932 Inst.addOperand(MCOperand::createReg(Reg));
1933 Inst.addOperand(MCOperand::createReg(Base));
1934 Inst.addOperand(MCOperand::createImm(Offset));
1939 static DecodeStatus DecodeFMem(MCInst &Inst,
1950 Inst.addOperand(MCOperand::createReg(Reg));
1951 Inst.addOperand(MCOperand::createReg(Base));
1952 Inst.addOperand(MCOperand::createImm(Offset));
1957 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
1968 Inst.addOperand(MCOperand::createReg(Reg));
1969 Inst.addOperand(MCOperand::createReg(Base));
1970 Inst.addOperand(MCOperand::createImm(Offset));
1975 static DecodeStatus DecodeFMem2(MCInst &Inst,
1986 Inst.addOperand(MCOperand::createReg(Reg));
1987 Inst.addOperand(MCOperand::createReg(Base));
1988 Inst.addOperand(MCOperand::createImm(Offset));
1993 static DecodeStatus DecodeFMem3(MCInst &Inst,
2004 Inst.addOperand(MCOperand::createReg(Reg));
2005 Inst.addOperand(MCOperand::createReg(Base));
2006 Inst.addOperand(MCOperand::createImm(Offset));
2011 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
2022 Inst.addOperand(MCOperand::createReg(Reg));
2023 Inst.addOperand(MCOperand::createReg(Base));
2024 Inst.addOperand(MCOperand::createImm(Offset));
2029 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
2038 Inst.addOperand(MCOperand::createReg(Reg));
2039 Inst.addOperand(MCOperand::createReg(Base));
2040 Inst.addOperand(MCOperand::createImm(Offset));
2045 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
2056 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
2057 Inst.addOperand(MCOperand::createReg(Rt));
2060 Inst.addOperand(MCOperand::createReg(Rt));
2061 Inst.addOperand(MCOperand::createReg(Base));
2062 Inst.addOperand(MCOperand::createImm(Offset));
2067 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
2074 Inst.addOperand(MCOperand::createReg(Mips::HWR29));
2078 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
2086 Inst.addOperand(MCOperand::createReg(Reg));
2090 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
2098 Inst.addOperand(MCOperand::createReg(Reg));
2102 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
2110 Inst.addOperand(MCOperand::createReg(Reg));
2114 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
2122 Inst.addOperand(MCOperand::createReg(Reg));
2126 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
2134 Inst.addOperand(MCOperand::createReg(Reg));
2138 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
2146 Inst.addOperand(MCOperand::createReg(Reg));
2150 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
2158 Inst.addOperand(MCOperand::createReg(Reg));
2162 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
2170 Inst.addOperand(MCOperand::createReg(Reg));
2174 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
2182 Inst.addOperand(MCOperand::createReg(Reg));
2186 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
2194 Inst.addOperand(MCOperand::createReg(Reg));
2198 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
2206 Inst.addOperand(MCOperand::createReg(Reg));
2210 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
2215 Inst.addOperand(MCOperand::createImm(BranchOffset));
2219 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst,
2224 Inst.addOperand(MCOperand::createImm(BranchOffset));
2228 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
2233 Inst.addOperand(MCOperand::createImm(JumpOffset));
2237 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
2243 Inst.addOperand(MCOperand::createImm(BranchOffset));
2247 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst,
2253 Inst.addOperand(MCOperand::createImm(BranchOffset));
2257 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
2263 Inst.addOperand(MCOperand::createImm(BranchOffset));
2267 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
2272 Inst.addOperand(MCOperand::createImm(BranchOffset));
2276 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
2281 Inst.addOperand(MCOperand::createImm(BranchOffset));
2285 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
2290 Inst.addOperand(MCOperand::createImm(BranchOffset));
2294 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst,
2300 Inst.addOperand(MCOperand::createImm(BranchOffset));
2304 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
2309 Inst.addOperand(MCOperand::createImm(JumpOffset));
2313 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst,
2318 Inst.addOperand(MCOperand::createImm(JumpOffset));
2322 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
2327 Inst.addOperand(MCOperand::createImm(1));
2329 Inst.addOperand(MCOperand::createImm(-1));
2331 Inst.addOperand(MCOperand::createImm(Value << 2));
2335 static DecodeStatus DecodeLi16Imm(MCInst &Inst,
2340 Inst.addOperand(MCOperand::createImm(-1));
2342 Inst.addOperand(MCOperand::createImm(Value));
2346 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
2350 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
2355 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
2360 Inst.addOperand(MCOperand::createImm(Value + Offset));
2365 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
2369 Inst.addOperand(MCOperand::createImm(Imm + Offset));
2373 static DecodeStatus DecodeInsSize(MCInst &Inst,
2380 int Pos = Inst.getOperand(2).getImm();
2382 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
2386 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
2388 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
2392 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
2394 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
2398 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
2408 Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
2412 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
2418 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
2422 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
2443 Inst.addOperand(MCOperand::createReg(Regs[i]));
2446 Inst.addOperand(MCOperand::createReg(Mips::RA));
2451 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
2456 switch(Inst.getOpcode()) {
2468 Inst.addOperand(MCOperand::createReg(Regs[i]));
2470 Inst.addOperand(MCOperand::createReg(Mips::RA));
2475 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
2479 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) ==
2489 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) ==
2494 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) ==
2501 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
2507 Inst.addOperand(MCOperand::createReg(Mips::A1));
2508 Inst.addOperand(MCOperand::createReg(Mips::A2));
2511 Inst.addOperand(MCOperand::createReg(Mips::A1));
2512 Inst.addOperand(MCOperand::createReg(Mips::A3));
2515 Inst.addOperand(MCOperand::createReg(Mips::A2));
2516 Inst.addOperand(MCOperand::createReg(Mips::A3));
2519 Inst.addOperand(MCOperand::createReg(Mips::A0));
2520 Inst.addOperand(MCOperand::createReg(Mips::S5));
2523 Inst.addOperand(MCOperand::createReg(Mips::A0));
2524 Inst.addOperand(MCOperand::createReg(Mips::S6));
2527 Inst.addOperand(MCOperand::createReg(Mips::A0));
2528 Inst.addOperand(MCOperand::createReg(Mips::A1));
2531 Inst.addOperand(MCOperand::createReg(Mips::A0));
2532 Inst.addOperand(MCOperand::createReg(Mips::A2));
2535 Inst.addOperand(MCOperand::createReg(Mips::A0));
2536 Inst.addOperand(MCOperand::createReg(Mips::A3));
2543 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
2545 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));