Searched refs:INSERT_SUBVECTOR (Results 1 - 16 of 16) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h401 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector
407 INSERT_SUBVECTOR, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp97 setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom);
188 setOperationAction(ISD::INSERT_SUBVECTOR, BoolV, Custom);
1565 case ISD::INSERT_SUBVECTOR: return LowerHvxInsertSubvector(Op, DAG);
H A DHexagonISelLowering.cpp1492 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR,
1541 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom);
2904 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp781 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
1350 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);
1432 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1620 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);
1753 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1754 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1784 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Legal);
1785 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Legal);
1988 setTargetDAGCombine(ISD::INSERT_SUBVECTOR);
5685 return DAG.getNode(ISD::INSERT_SUBVECTOR, d
[all...]
H A DX86ISelDAGToDAG.cpp718 if (Root->getOpcode() == ISD::INSERT_SUBVECTOR &&
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp283 case ISD::INSERT_SUBVECTOR: return "insert_subvector";
H A DLegalizeVectorOps.cpp1091 ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), Src,
1151 ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), Src,
H A DLegalizeVectorTypes.cpp834 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
1147 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx);
3196 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT),
3199 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT),
4292 ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp,
H A DDAGCombiner.cpp1612 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
17487 // Legalizing INSERT_SUBVECTOR is tricky - you basically have to
17493 VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1,
18285 // Helper that peeks through INSERT_SUBVECTOR/CONCAT_VECTORS to find
18288 if (V.getOpcode() == ISD::INSERT_SUBVECTOR &&
18633 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) {
19591 // i.e. INSERT_SUBVECTOR UNDEF (BITCAST N1) N2 ->
19592 // BITCAST (INSERT_SUBVECTOR UNDEF N1 N2)
19605 // i.e. INSERT_SUBVECTOR (BITCAST N0) (BITCAST N1) N2 ->
19606 // BITCAST (INSERT_SUBVECTOR N
[all...]
H A DSelectionDAG.cpp2624 case ISD::INSERT_SUBVECTOR: {
3948 case ISD::INSERT_SUBVECTOR: {
5441 // EXTRACT_SUBVECTOR of INSERT_SUBVECTOR is often created
5443 if (N1.getOpcode() == ISD::INSERT_SUBVECTOR && N2 == N1.getOperand(2) &&
5611 case ISD::INSERT_SUBVECTOR: {
9467 /// Widen the vector up to the next power of two using INSERT_SUBVECTOR.
9472 return getNode(ISD::INSERT_SUBVECTOR, DL, WideVT, getUNDEF(WideVT), N,
H A DTargetLowering.cpp921 case ISD::INSERT_SUBVECTOR: {
2325 case ISD::INSERT_SUBVECTOR: {
2347 TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
H A DLegalizeDAG.cpp3019 case ISD::INSERT_SUBVECTOR:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp272 case ISD::INSERT_SUBVECTOR:
338 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3i32, Custom);
339 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3f32, Custom);
340 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i32, Custom);
341 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4f32, Custom);
344 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5i32, Custom);
345 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5f32, Custom);
346 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i32, Custom);
347 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8f32, Custom);
534 case ISD::INSERT_SUBVECTOR
[all...]
H A DAMDGPUISelLowering.cpp1442 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad,
1444 Join = DAG.getNode(HiVT.isVector() ? ISD::INSERT_SUBVECTOR
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp545 if (SV.getOpcode() != ISD::INSERT_SUBVECTOR)
H A DAArch64ISelLowering.cpp6513 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),

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