Searched refs:INLINEASM (Results 1 - 25 of 35) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp86 case ISD::INLINEASM: break;
123 case ISD::INLINEASM: break;
449 case ISD::INLINEASM:
552 case ISD::INLINEASM:
H A DInstrEmitter.cpp1045 case ISD::INLINEASM:
1054 : TargetOpcode::INLINEASM;
H A DSelectionDAGDumper.cpp174 case ISD::INLINEASM: return "inlineasm";
H A DScheduleDAGFast.cpp482 if (Node->getOpcode() == ISD::INLINEASM ||
H A DScheduleDAGRRList.cpp716 case ISD::INLINEASM:
1362 if (Node->getOpcode() == ISD::INLINEASM ||
H A DSelectionDAGISel.cpp2244 SDValue New = CurDAG->getNode(Branch ? ISD::INLINEASM_BR : ISD::INLINEASM, DL, VTs, Ops);
2810 case ISD::INLINEASM:
H A DFastISel.cpp1328 TII.get(TargetOpcode::INLINEASM))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVectorPrint.cpp102 BuildMI(*MBB, I, DL, QII->get(TargetOpcode::INLINEASM))
H A DHexagonMachineScheduler.cpp114 case TargetOpcode::INLINEASM:
170 case TargetOpcode::INLINEASM:
H A DHexagonInstrInfo.cpp2339 case TargetOpcode::INLINEASM:
2793 case Hexagon::INLINEASM:
4306 if (BranchRelaxAsmLarge && MI.getOpcode() == Hexagon::INLINEASM) {
H A DHexagonISelLowering.cpp635 if ((Op.getOpcode() != ISD::INLINEASM &&
1353 setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
2885 // Handle INLINEASM first.
2886 if (Opc == ISD::INLINEASM || Opc == ISD::INLINEASM_BR)
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h710 /// INLINEASM - Represents an inline asm block. This node always has two
725 INLINEASM, enumerator in enum:llvm::ISD::NodeType
H A DMachineInstr.h1086 return getOpcode() == TargetOpcode::INLINEASM ||
1477 /// INLINEASM instruction, in which case the side effect property is encoded
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSERegisterInfo.cpp103 case Mips::INLINEASM: {
H A DMipsInstrInfo.cpp580 case TargetOpcode::INLINEASM:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp310 case TargetOpcode::INLINEASM:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp331 case ISD::INLINEASM:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyAsmPrinter.cpp393 assert(MI->getOpcode() == WebAssembly::INLINEASM);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp490 case TargetOpcode::INLINEASM:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp487 if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Bitcode/Reader/
H A DBitcodeAnalyzer.cpp213 STRINGIFY_CODE(CST_CODE, INLINEASM)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp424 case PPC::INLINEASM:
H A DPPCRegisterInfo.cpp1148 else if (OpC != TargetOpcode::INLINEASM &&
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp482 case TargetOpcode::INLINEASM:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FloatingPoint.cpp1491 case TargetOpcode::INLINEASM:

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