Searched refs:GP (Results 1 - 25 of 27) sorted by relevance

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/freebsd-11-stable/lib/libc/mips/gen/
H A D_setjmp.S193 * our caller's GP.
/freebsd-11-stable/sys/mips/include/
H A Dregnum.h93 #define GP 28 macro
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsABIInfo.cpp87 return ArePtrs64bit() ? Mips::GP_64 : Mips::GP;
H A DMipsTargetStreamer.cpp42 : MCTargetStreamer(S), GPReg(Mips::GP), ModuleDirectiveAllowed(true) {
H A DMipsMCCodeEmitter.cpp846 MI.getOperand(OpNo).getReg() == Mips::GP &&
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp175 // For mno-abicalls, GP is a program invariant!
177 Reserved.set(Mips::GP);
234 // Reserve GP if small section is used.
236 Reserved.set(Mips::GP);
H A DMipsOptimizePICCall.cpp52 cl::init(true), cl::desc("Erase GP Operand"),
161 /// Search MI's operands for register GP and erase it.
168 unsigned Reg = Ty == MVT::i32 ? Mips::GP : Mips::GP_64;
H A DMipsCallLowering.cpp633 Register(Mips::GP),
635 MIB.addDef(Mips::GP, RegState::Implicit);
H A DMipsISelLowering.h492 DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
H A DMicroMipsSizeReduction.cpp383 Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP,
/freebsd-11-stable/contrib/gcc/config/ia64/
H A Dcrtend.asm59 * Note that we require __do_global_ctors_aux to preserve the GP,
H A Dlib1funcs.asm198 // Transfer result to GP registers.
255 // Transfer result to GP registers.
308 // Transfer result to GP registers.
366 // Transfer result to GP registers.
H A Dcrtbegin.asm87 * Note that we require __do_global_dtors_aux to preserve the GP,
/freebsd-11-stable/sys/mips/mips/
H A Dexception.S295 SAVE_REG(gp, GP, sp) ;\
365 RESTORE_REG(gp, GP, sp) ;\
468 SAVE_U_PCB_REG(gp, GP, k1)
480 PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP
558 RESTORE_U_PCB_REG(gp, GP, k1)
715 SAVE_U_PCB_REG(gp, GP, k1)
742 PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP
834 RESTORE_U_PCB_REG(gp, GP, k1)
H A Dswtch.S128 RESTORE_U_PCB_REG(gp, GP, k1)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCRegisterInfo.cpp144 Reserved.set(ARC::GP);
/freebsd-11-stable/stand/pc98/btx/btx/
H A Dbtx.S339 push $0xd # Int 0xd: #GP
679 leal -0x18(%esi),%edi # Kernel stack GP regs
681 movl $MEM_ESPR-0x0c,%esi # Real mode stack GP regs
682 movl $8,%ecx # Copy GP regs from
/freebsd-11-stable/stand/i386/btx/btx/
H A Dbtx.S337 push $0xd # Int 0xd: #GP
653 leal -0x18(%esi),%edi # Kernel stack GP regs
655 movl $MEM_ESPR-0x0c,%esi # Real mode stack GP regs
656 movl $8,%ecx # Copy GP regs from
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp117 ARC::R21, ARC::R22, ARC::R23, ARC::R24, ARC::R25, ARC::GP, ARC::FP,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp158 Reserved.set(Hexagon::GP); // C11
/freebsd-11-stable/contrib/binutils/gas/config/
H A Dtc-score.c37 #define GP 28 macro
4340 inst.instruction |= GP << 15;
4409 /* GP instruction can not do optimization, only can do relax between
4458 inst.instruction |= GP << 15;
4841 /* Only at the first time determining whether GP instruction relax should be done,
4854 /* In this function, we determine whether GP instruction should do relaxation,
4967 /* Handle specially for GP instruction. for, judge_size_before_relax() has already determine
4968 whether the GP instruction should do relax. */
6236 sprintf (insn_str, "ld_i32hi r%d, %s", GP, GP_DISP_LABEL);
6240 sprintf (insn_str, "ld_i32lo r%d, %s", GP, GP_DISP_LABE
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp652 /* 8 */ USR, PC, UGP, GP,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.cpp647 // Look for GP-relative fixups.
656 if (*U == Hexagon::GP)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1369 && (getMemBase()->getGPR32Reg() == Mips::GP);
2158 // Try to create 16-bit GP relative load instruction.
2171 (BaseReg.getReg() == Mips::GP ||
2174 TOut.emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset,
3226 case Mips::K1: return Mips::GP;
3227 case Mips::GP: return Mips::SP;
5415 case Mips::F28: return Mips::GP;
5454 case Mips::COP028: return Mips::GP;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp1834 Inst.addOperand(MCOperand::createReg(Mips::GP));

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