Searched refs:FP_TO_FP16 (Results 1 - 16 of 16) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h631 /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions
635 FP16_TO_FP, FP_TO_FP16, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.h463 FP_TO_FP16,
H A DAMDGPUISelLowering.cpp302 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Custom);
303 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom);
1150 case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG);
2616 return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0);
2619 // There is a generic expand for FP_TO_FP16 with unsafe fast math.
4320 NODE_NAME_CASE(FP_TO_FP16)
4454 case AMDGPUISD::FP_TO_FP16:
4602 case AMDGPUISD::FP_TO_FP16:
H A DSIISelLowering.cpp485 setOperationAction(ISD::FP_TO_FP16, MVT::i16, Promote);
486 AddPromotedToType(ISD::FP_TO_FP16, MVT::i16, MVT::i32);
4600 SDValue FpToFp16 = DAG.getNode(ISD::FP_TO_FP16, DL, MVT::i32, Src);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp777 case ISD::FP_TO_FP16: // Same as FP_ROUND for softening purposes
822 // We actually deal with the partially-softened FP_TO_FP16 node too, which
824 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16 ||
831 EVT FloatRVT = N->getOpcode() == ISD::FP_TO_FP16 ? MVT::f16 : RVT;
1941 return ISD::FP_TO_FP16;
2091 case ISD::FP_TO_FP16:
H A DSelectionDAGDumper.cpp344 case ISD::FP_TO_FP16: return "fp_to_fp16";
H A DLegalizeDAG.cpp1001 case ISD::FP_TO_FP16:
3222 case ISD::FP_TO_FP16:
3223 LLVM_DEBUG(dbgs() << "Legalizing FP_TO_FP16\n");
3228 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3234 DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal));
4135 case ISD::FP_TO_FP16: {
H A DLegalizeIntegerTypes.cpp124 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
321 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp));
H A DSelectionDAG.cpp4505 case ISD::FP_TO_FP16: {
H A DDAGCombiner.cpp1618 case ISD::FP_TO_FP16: return visitFP_TO_FP16(N);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp106 setOperationAction(ISD::FP_TO_FP16, T, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp453 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
455 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp165 ISD::FP_TO_FP16};
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp179 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
182 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1350 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1356 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp367 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
374 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
375 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
376 setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand);
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