Searched refs:FP (Results 1 - 25 of 107) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetOptionsImpl.cpp33 StringRef FP = F.getFnAttribute("frame-pointer").getValueAsString();
34 if (FP == "all")
36 if (FP == "non-leaf")
38 if (FP == "none")
H A DTargetSubtargetInfo.cpp22 const InstrStage *IS, const unsigned *OC, const unsigned *FP)
23 : MCSubtargetInfo(TT, CPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {
17 TargetSubtargetInfo( const Triple &TT, StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetSubTypeKV> PD, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) argument
H A DRegisterUsageInfo.cpp60 const Function &FP, ArrayRef<uint32_t> RegMask) {
61 RegMasks[&FP] = RegMask;
65 PhysicalRegisterUsageInfo::getRegUsageInfo(const Function &FP) { argument
66 auto It = RegMasks.find(&FP);
59 storeUpdateRegUsageInfo( const Function &FP, ArrayRef<uint32_t> RegMask) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp136 : FP(P), TRI(T) {}
138 const FlowPattern &FP; member in struct:__anon2238::PrintFP
145 OS << "{ SplitB:" << PrintMB(P.FP.SplitB)
146 << ", PredR:" << printReg(P.FP.PredR, &P.TRI)
147 << ", TrueB:" << PrintMB(P.FP.TrueB)
148 << ", FalseB:" << PrintMB(P.FP.FalseB)
149 << ", JoinB:" << PrintMB(P.FP.JoinB) << " }";
178 FlowPattern &FP);
186 bool isValid(const FlowPattern &FP) const;
189 const FlowPattern &FP) cons
238 matchFlowPattern(MachineBasicBlock *B, MachineLoop *L, FlowPattern &FP) argument
810 updatePhiNodes(MachineBasicBlock *WhereB, const FlowPattern &FP) argument
859 convert(const FlowPattern &FP) argument
1025 simplifyFlowGraph(const FlowPattern &FP) argument
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/freebsd-11-stable/contrib/binutils/opcodes/
H A Dalpha-opc.c350 #define FP(oo,fff) FP_(oo,fff), FP_MASK
667 { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } },
668 { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 },
669 { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 },
670 { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } },
671 { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } },
672 { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 },
673 { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 },
674 { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 },
675 { "sqrtt/m", FP(
347 #define FP macro
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/freebsd-11-stable/sys/arm/include/
H A Dstack.h53 #define FP 11 macro
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterUsageInfo.h51 void storeUpdateRegUsageInfo(const Function &FP,
56 ArrayRef<uint32_t> getRegUsageInfo(const Function &FP);
/freebsd-11-stable/etc/rc.d/
H A Dipsec50 ${ipsec_program} -FP
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiFrameLowering.cpp88 // st %fp,-4[*%sp] !push old FP
89 // add %sp,8,%fp !generate new FP
111 // Push old FP
114 .addReg(Lanai::FP)
120 // Generate new FP
122 BuildMI(MBB, MBBI, DL, LII.get(Lanai::ADD_I_LO), Lanai::FP)
187 .addReg(Lanai::FP)
191 BuildMI(MBB, MBBI, DL, LII.get(Lanai::LDW_RI), Lanai::FP)
192 .addReg(Lanai::FP)
211 // Reserve 4 bytes for the saved FP
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H A DLanaiDelaySlotFiller.cpp109 RI->getOperand(0).getReg() == Lanai::FP &&
111 RI->getOperand(1).getReg() == Lanai::FP &&
118 RI->getOperand(1).getReg() == Lanai::FP);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp42 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7,
52 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7,
90 Reserved.set(MSP430::FP);
115 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FP : MSP430::SP);
124 Offset += 2; // Skip the saved FP
159 return TFI->hasFP(MF) ? MSP430::FP : MSP430::SP;
H A DMSP430FrameLowering.cpp65 // Save FP into the appropriate stack slot...
67 .addReg(MSP430::FP, RegState::Kill);
69 // Update FP with the new base value...
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP)
76 I->addLiveIn(MSP430::FP);
134 // pop FP.
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP);
157 TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::FP);
292 // Create a frame entry for the FP register that must be saved.
297 "Slot for FP registe
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/freebsd-11-stable/tools/regression/ipsec/
H A Dipsec6.t66 setkey -FP
101 setkey -FP
H A Dipsec.t66 setkey -FP
101 setkey -FP
/freebsd-11-stable/sys/arm/arm/
H A Ddb_trace.c88 state->registers[SP], state->registers[FP]);
92 ~((1 << SP) | (1 << FP) | (1 << LR) | (1 << PC));
162 state.registers[FP] = ctx->pcb_regs.sf_r11;
182 state.registers[FP] = (uint32_t)__builtin_frame_address(0);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Support/
H A DCodeGen.h71 enum FP {All, NonLeaf, None}; enum in namespace:llvm::FramePointer
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DRegionPass.h119 Pass *FP = static_cast<Pass *>(PassVector[N]);
120 return FP;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyInstPrinter.cpp185 static std::string toString(const APFloat &FP) { argument
187 if (FP.isNaN() && !FP.bitwiseIsEqual(APFloat::getQNaN(FP.getSemantics())) &&
188 !FP.bitwiseIsEqual(
189 APFloat::getQNaN(FP.getSemantics(), /*Negative=*/true))) {
190 APInt AI = FP.bitcastToAPInt();
201 auto Written = FP.convertToHexString(
/freebsd-11-stable/contrib/llvm-project/clang/lib/AST/Interp/
H A DEvalEmitter.cpp123 const Pointer &FP = Ptr.atField(F.Offset);
125 if (FP.isActive()) {
127 TYPE_SWITCH(*T, Ok &= ReturnValue<T>(FP.deref<T>(), Value));
129 Ok &= Composite(FieldTy, FP, Value);
145 const Pointer &FP = Ptr.atField(FD->Offset);
149 TYPE_SWITCH(*T, Ok &= ReturnValue<T>(FP.deref<T>(), Value));
151 Ok &= Composite(FieldTy, FP, Value);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp190 // Reserve FP if this function should have a dedicated frame pointer register.
195 Reserved.set(Mips::FP);
290 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
306 unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64; local
315 if (!MF.getRegInfo().canReserveReg(FP))
/freebsd-11-stable/contrib/llvm-project/libcxx/src/
H A Dchrono.cpp161 typedef steady_clock::rep (*FP)(); typedef in class:chrono::steady_clock
164 FP
177 static FP fp = init_steady_clock();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h55 case Lanai::FP:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/IR/
H A DLegacyPassManager.cpp376 FPPassManager *FP = static_cast<FPPassManager *>(PassManagers[N]);
377 return FP;
1392 FunctionPass *FP = getContainedPass(Index); local
1393 AnalysisResolver *AR = FP->getResolver();
1437 FunctionPass *FP = getContainedPass(Index); local
1438 FP->dumpPassStructure(Offset + 1);
1439 dumpLastUses(FP, Offset+1);
1468 FunctionPass *FP = getContainedPass(Index); local
1471 llvm::TimeTraceScope PassScope("RunPass", FP->getPassName());
1473 dumpPassInfo(FP, EXECUTION_MS
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/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterContext_x86.h272 MMSReg stmm[8]; // 8*16 bytes for each FP-reg = 128 bytes
310 FP = 1, member in class:lldb_private::XSAVE_HDR::XFeature
311 SSE = FP << 1,
/freebsd-11-stable/sys/crypto/des/
H A Ddes_enc.c162 FP(r,l);
274 FP(r,l);
294 FP(r,l);

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