1//===- RegisterUsageInfo.cpp - Register Usage Information Storage ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// This pass is required to take advantage of the interprocedural register
10/// allocation infrastructure.
11///
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/RegisterUsageInfo.h"
15#include "llvm/ADT/SmallVector.h"
16#include "llvm/CodeGen/MachineOperand.h"
17#include "llvm/CodeGen/TargetRegisterInfo.h"
18#include "llvm/CodeGen/TargetSubtargetInfo.h"
19#include "llvm/IR/Function.h"
20#include "llvm/IR/Module.h"
21#include "llvm/Pass.h"
22#include "llvm/Support/CommandLine.h"
23#include "llvm/Support/raw_ostream.h"
24#include "llvm/Target/TargetMachine.h"
25#include <algorithm>
26#include <cassert>
27#include <cstdint>
28#include <utility>
29#include <vector>
30
31using namespace llvm;
32
33static cl::opt<bool> DumpRegUsage(
34    "print-regusage", cl::init(false), cl::Hidden,
35    cl::desc("print register usage details collected for analysis."));
36
37INITIALIZE_PASS(PhysicalRegisterUsageInfo, "reg-usage-info",
38                "Register Usage Information Storage", false, true)
39
40char PhysicalRegisterUsageInfo::ID = 0;
41
42void PhysicalRegisterUsageInfo::setTargetMachine(const LLVMTargetMachine &TM) {
43  this->TM = &TM;
44}
45
46bool PhysicalRegisterUsageInfo::doInitialization(Module &M) {
47  RegMasks.grow(M.size());
48  return false;
49}
50
51bool PhysicalRegisterUsageInfo::doFinalization(Module &M) {
52  if (DumpRegUsage)
53    print(errs());
54
55  RegMasks.shrink_and_clear();
56  return false;
57}
58
59void PhysicalRegisterUsageInfo::storeUpdateRegUsageInfo(
60    const Function &FP, ArrayRef<uint32_t> RegMask) {
61  RegMasks[&FP] = RegMask;
62}
63
64ArrayRef<uint32_t>
65PhysicalRegisterUsageInfo::getRegUsageInfo(const Function &FP) {
66  auto It = RegMasks.find(&FP);
67  if (It != RegMasks.end())
68    return makeArrayRef<uint32_t>(It->second);
69  return ArrayRef<uint32_t>();
70}
71
72void PhysicalRegisterUsageInfo::print(raw_ostream &OS, const Module *M) const {
73  using FuncPtrRegMaskPair = std::pair<const Function *, std::vector<uint32_t>>;
74
75  SmallVector<const FuncPtrRegMaskPair *, 64> FPRMPairVector;
76
77  // Create a vector of pointer to RegMasks entries
78  for (const auto &RegMask : RegMasks)
79    FPRMPairVector.push_back(&RegMask);
80
81  // sort the vector to print analysis in alphabatic order of function name.
82  llvm::sort(
83      FPRMPairVector,
84      [](const FuncPtrRegMaskPair *A, const FuncPtrRegMaskPair *B) -> bool {
85        return A->first->getName() < B->first->getName();
86      });
87
88  for (const FuncPtrRegMaskPair *FPRMPair : FPRMPairVector) {
89    OS << FPRMPair->first->getName() << " "
90       << "Clobbered Registers: ";
91    const TargetRegisterInfo *TRI
92        = TM->getSubtarget<TargetSubtargetInfo>(*(FPRMPair->first))
93          .getRegisterInfo();
94
95    for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
96      if (MachineOperand::clobbersPhysReg(&(FPRMPair->second[0]), PReg))
97        OS << printReg(PReg, TRI) << " ";
98    }
99    OS << "\n";
100  }
101}
102