Searched refs:FCANONICALIZE (Results 1 - 11 of 11) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h373 FCANONICALIZE, enumerator in enum:llvm::ISD::NodeType
H A DBasicTTIImpl.h1247 ISDs.push_back(ISD::FCANONICALIZE);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp263 case ISD::FCANONICALIZE: return "fcanonicalize";
H A DLegalizeVectorTypes.cpp104 case ISD::FCANONICALIZE:
896 case ISD::FCANONICALIZE:
1974 case ISD::FCANONICALIZE:
2845 case ISD::FCANONICALIZE:
H A DLegalizeVectorOps.cpp454 case ISD::FCANONICALIZE:
H A DLegalizeFloatTypes.cpp2123 case ISD::FCANONICALIZE: R = PromoteFloatRes_UnaryOp(N); break;
H A DTargetLowering.cpp6329 Quiet0 = DAG.getNode(ISD::FCANONICALIZE, dl, VT, Quiet0,
6333 Quiet1 = DAG.getNode(ISD::FCANONICALIZE, dl, VT, Quiet1,
H A DSelectionDAGBuilder.cpp6193 case Intrinsic::canonicalize: Opcode = ISD::FCANONICALIZE; break;
H A DSelectionDAG.cpp4105 case ISD::FCANONICALIZE:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp632 setOperationAction(ISD::FCANONICALIZE, MVT::v2f16, Legal);
661 setOperationAction(ISD::FCANONICALIZE, MVT::v4f16, Custom);
737 setTargetDAGCombine(ISD::FCANONICALIZE);
4082 case ISD::FCANONICALIZE:
8599 case ISD::FCANONICALIZE:
8744 if (Opcode == ISD::FCANONICALIZE)
8973 NewElts[I] = DAG.getNode(ISD::FCANONICALIZE, SL, EltVT, Op);
9006 SDValue Canon0 = DAG.getNode(ISD::FCANONICALIZE, SL, VT,
10057 case ISD::FCANONICALIZE:
H A DAMDGPUISelLowering.cpp432 setOperationAction(ISD::FCANONICALIZE, VT, Expand);
526 case ISD::FCANONICALIZE:
3810 case ISD::FCANONICALIZE:

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