Searched refs:DstRC (Results 1 - 25 of 32) sorted by relevance

12

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.h61 const TargetRegisterClass *DstRC,
H A DAVRRegisterInfo.cpp279 const TargetRegisterClass *DstRC,
287 return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, NewRC, LIS);
276 shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp181 const TargetRegisterClass *DstRC = Register::isVirtualRegister(DstReg) local
185 return std::make_pair(SrcRC, DstRC);
189 const TargetRegisterClass *DstRC,
191 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) &&
196 const TargetRegisterClass *DstRC,
198 return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) &&
199 TRI.hasVectorRegisters(DstRC);
261 const TargetRegisterClass *SrcRC, *DstRC; local
262 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI);
264 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TR
188 isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, const TargetRegisterClass *DstRC, const SIRegisterInfo &TRI) argument
195 isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, const TargetRegisterClass *DstRC, const SIRegisterInfo &TRI) argument
[all...]
H A DAMDGPUInstructionSelector.cpp498 const TargetRegisterClass *DstRC = local
500 if (!DstRC)
503 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8);
517 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))
556 const TargetRegisterClass *DstRC = local
558 if (DstRC && !RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI))
605 const TargetRegisterClass *DstRC = local
607 if (!DstRC)
623 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MR
[all...]
H A DSIRegisterInfo.h239 const TargetRegisterClass *DstRC,
H A DSIInstrInfo.cpp487 const TargetRegisterClass *DstRC = Register::isVirtualRegister(Reg) local
491 return (NumLoads * (RI.getRegSizeInBits(*DstRC) / 8)) <= LoadClusterThreshold;
973 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
975 if (RI.hasAGPRs(DstRC))
977 if (RI.getRegSizeInBits(*DstRC) == 32) {
978 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
979 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) {
981 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) {
2177 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg); local
[all...]
H A DSIInstrInfo.h242 // Returns an opcode that can be used to move a value to a \p DstRC
244 // DstRC, then AMDGPU::COPY is returned.
245 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
884 const TargetRegisterClass *DstRC,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.h64 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
H A DHexagonRegisterInfo.cpp242 const TargetRegisterClass *DstRC, unsigned DstSubReg,
253 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID();
240 shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const argument
H A DHexagonGenInsert.cpp686 const TargetRegisterClass *DstRC = MRI->getRegClass(DstR);
690 if (!isIntClass(DstRC) || !isIntClass(SrcRC) || !isIntClass(InsRC))
693 if (DstRC != SrcRC)
695 if (DstRC == InsRC)
698 if (DstRC == &Hexagon::DoubleRegsRegClass)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.h86 /// SrcRC and DstRC will be morphed into NewRC if this returns true.
90 const TargetRegisterClass *DstRC,
H A DSystemZRegisterInfo.cpp343 const TargetRegisterClass *DstRC,
351 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
340 shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp154 const TargetRegisterClass *DstRC,
159 if (DstRC == SrcRC)
184 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA,
187 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx);
189 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx);
190 return !TRI.getCommonSubClass(SrcRC, DstRC);
438 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); local
439 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO);
487 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); local
488 *CrossCopy = isCrossCopy(*MRI, MI, DstRC, M
152 isCrossCopy(const MachineRegisterInfo &MRI, const MachineInstr &MI, const TargetRegisterClass *DstRC, const MachineOperand &MO) argument
[all...]
H A DPeepholeOptimizer.cpp474 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
475 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
476 if (!DstRC)
582 MRI->constrainRegClass(DstReg, DstRC);
H A DRegisterCoalescer.cpp466 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); local
474 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
481 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
485 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
488 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
503 CrossClass = NewRC != DstRC || NewRC != SrcRC;
1325 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); local
1327 TRI->getCommonSubClass(DefRC, DstRC);
1798 auto DstRC = MRI->getRegClass(CP.getDstReg()); local
1803 std::swap(SrcRC, DstRC);
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp109 const TargetRegisterClass *DstRC,
249 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg); local
251 if (SrcRC != DstRC) {
253 Register ExtSrc = MRI.createVirtualRegister(DstRC);
277 const TargetRegisterClass *DstRC = local
287 if (DstRC != SrcRC) {
288 I.getOperand(1).setSubReg(getSubRegIndex(DstRC));
297 if (!OldRC || !DstRC->hasSubClassEq(OldRC)) {
298 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
681 // Returns true if DstRC live
683 canTurnIntoCOPY(const TargetRegisterClass *DstRC, const TargetRegisterClass *SrcRC) argument
690 selectTurnIntoCOPY( MachineInstr &I, MachineRegisterInfo &MRI, const unsigned DstReg, const TargetRegisterClass *DstRC, const unsigned SrcReg, const TargetRegisterClass *SrcRC) const argument
727 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); local
809 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); local
902 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); local
1216 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI); local
1256 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp120 const TargetRegisterClass *DstRC = &PPC::VSLRCRegClass; local
127 Register NewVReg = MRI.createVirtualRegister(DstRC);
H A DPPCVSXSwapRemoval.cpp898 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); local
899 Register NewVReg = MRI->createVirtualRegister(DstRC);
912 if (DstRC == &PPC::VRRCRegClass) {
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DFastISelEmitter.cpp204 const CodeGenRegisterClass *DstRC = nullptr;
282 if (DstRC) {
283 if (DstRC != RC && !DstRC->hasSubClass(RC))
286 DstRC = RC;
489 const CodeGenRegisterClass *DstRC = nullptr;
497 DstRC = &Target.getRegisterClass(Op0Rec);
498 if (!DstRC)
537 DstRC))
587 DstRC,
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp175 auto DstRC = MRI.getRegClass(DstReg); local
176 if (SrcRC == DstRC) {
H A DCombinerHelper.cpp96 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); local
100 if ((SrcRC == DstRC) && (SrcBank == DstBank))
103 if (!DstBank && !DstRC)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstructionSelector.cpp100 const TargetRegisterClass *DstRC,
681 const TargetRegisterClass *DstRC; local
682 std::tie(SrcRC, DstRC) = getRegClassesForCopy(I, TII, MRI, TRI, RBI);
684 if (!DstRC) {
721 unsigned DstSize = TRI.getRegSizeInBits(*DstRC);
735 if (!getSubRegForClass(DstRC, TRI, SubReg)) {
741 selectSubregisterCopy(I, MRI, RBI, SrcReg, SubregRC, DstRC, SubReg);
774 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
2055 const TargetRegisterClass *DstRC = local
2057 if (!DstRC)
2380 const TargetRegisterClass *DstRC = local
2778 emitScalarToVector( unsigned EltSize, const TargetRegisterClass *DstRC, Register Scalar, MachineIRBuilder &MIRBuilder) const argument
2912 const TargetRegisterClass *DstRC = local
3398 const TargetRegisterClass *DstRC = local
3984 const TargetRegisterClass *DstRC = &AArch64::FPR128RegClass; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h205 /// SrcRC and DstRC will be morphed into NewRC if this returns true
209 const TargetRegisterClass *DstRC,
H A DARMBaseRegisterInfo.cpp839 const TargetRegisterClass *DstRC,
851 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 &&
860 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);
836 shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; local
161 DstRC = MRI->getRegClass(VRBase);
165 DstRC = UseRC;
167 DstRC = TLI->getRegClassFor(VT, Node->isDivergent());
176 VRBase = MRI->createVirtualRegister(DstRC);
614 const TargetRegisterClass *DstRC =
616 Register NewVReg = MRI->createVirtualRegister(DstRC);

Completed in 505 milliseconds

12